1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture

Yongsam Moon; Yong Ho Cho; Hyun Bae Lee; Byung Hoon Jeong; Seok Hun Hyun; Byung Chul Kim; In Chul Jeong; Seong Young Seo; Jun Ho Shin; Seok Woo Choi; Ho Sung Song; Jung Hwan Choi; Kye Hyun Kyung; Young Hyun Jun; Kinam Kim

doi:10.1109/ISSCC.2009.4977341

1.2V 1.6Gb/s 56nm 6F² 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture

Yongsam Moon, Yong Ho Cho, Hyun Bae Lee, Byung Hoon Jeong, Seok Hun Hyun, Byung Chul Kim, In Chul Jeong, Seong Young Seo, Jun Ho Shin, Seok Woo Choi, Ho Sung Song, Jung Hwan Choi, Kye Hyun Kyung, Young Hyun Jun, Kinam Kim

School of Electrical and Computer Engineering

Samsung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

23 Scopus citations

Original language	English
Title of host publication	2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009
DOIs	https://doi.org/10.1109/ISSCC.2009.4977341
State	Published - 2009
Event	2009 IEEE International Solid-State Circuits Conference ISSCC 2009 - San Francisco, CA, United States Duration: 8 Feb 2009 → 12 Feb 2009

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Conference

Conference	2009 IEEE International Solid-State Circuits Conference ISSCC 2009
Country/Territory	United States
City	San Francisco, CA
Period	8/02/09 → 12/02/09

Access to Document

10.1109/ISSCC.2009.4977341

Cite this

Moon, Y., Cho, Y. H., Lee, H. B., Jeong, B. H., Hyun, S. H., Kim, B. C., Jeong, I. C., Seo, S. Y., Shin, J. H., Choi, S. W., Song, H. S., Choi, J. H., Kyung, K. H., Jun, Y. H., & Kim, K. (2009). 1.2V 1.6Gb/s 56nm 6F² 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. In 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009 Article 4977341 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2009.4977341

@inproceedings{b23cb3b2de67458fadac0d47b16fe8c5,

title = "1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture",

author = "Yongsam Moon and Cho, {Yong Ho} and Lee, {Hyun Bae} and Jeong, {Byung Hoon} and Hyun, {Seok Hun} and Kim, {Byung Chul} and Jeong, {In Chul} and Seo, {Seong Young} and Shin, {Jun Ho} and Choi, {Seok Woo} and Song, {Ho Sung} and Choi, {Jung Hwan} and Kyung, {Kye Hyun} and Jun, {Young Hyun} and Kinam Kim",

year = "2009",

doi = "10.1109/ISSCC.2009.4977341",

language = "English",

isbn = "1424434580",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

booktitle = "2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009",

note = "2009 IEEE International Solid-State Circuits Conference ISSCC 2009 ; Conference date: 08-02-2009 Through 12-02-2009",

}

Moon, Y, Cho, YH, Lee, HB, Jeong, BH, Hyun, SH, Kim, BC, Jeong, IC, Seo, SY, Shin, JH, Choi, SW, Song, HS, Choi, JH, Kyung, KH, Jun, YH & Kim, K 2009, 1.2V 1.6Gb/s 56nm 6F² 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. in 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009., 4977341, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 2009 IEEE International Solid-State Circuits Conference ISSCC 2009, San Francisco, CA, United States, 8/02/09. https://doi.org/10.1109/ISSCC.2009.4977341

1.2V 1.6Gb/s 56nm 6F² 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. / Moon, Yongsam; Cho, Yong Ho; Lee, Hyun Bae et al.
2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009. 2009. 4977341 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - 1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture

AU - Moon, Yongsam

AU - Cho, Yong Ho

AU - Lee, Hyun Bae

AU - Jeong, Byung Hoon

AU - Hyun, Seok Hun

AU - Kim, Byung Chul

AU - Jeong, In Chul

AU - Seo, Seong Young

AU - Shin, Jun Ho

AU - Choi, Seok Woo

AU - Song, Ho Sung

AU - Choi, Jung Hwan

AU - Kyung, Kye Hyun

AU - Jun, Young Hyun

AU - Kim, Kinam

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M3 - Conference contribution

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SN - 1424434580

SN - 9781424434589

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

BT - 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009

T2 - 2009 IEEE International Solid-State Circuits Conference ISSCC 2009

Y2 - 8 February 2009 through 12 February 2009

ER -

Moon Y, Cho YH, Lee HB, Jeong BH, Hyun SH, Kim BC et al. 1.2V 1.6Gb/s 56nm 6F² 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. In 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009. 2009. 4977341. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2009.4977341