1Gbps transceiver with receiver-end deskewing capability using non-uniform tracked oversampling and a 250-750MHz four-phase DLL

Yongsam Moon; Deog Kyoon Jeong

1Gbps transceiver with receiver-end deskewing capability using non-uniform tracked oversampling and a 250-750MHz four-phase DLL

Yongsam Moon, Deog Kyoon Jeong

School of Electrical and Computer Engineering

Seoul National University

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

This paper describes a low power, 1Gbps, CMOS link with measured bit error rate (BER) < 10^-14. To obtain the low BER, skew between clock and data is detected and removed by using non-uniform tracked over-sampling technique with a high-resolution phase control. A delay-locked loop (DLL) with a wide operating frequency range of 250-750MHz generates four phase sampling clocks.

Original language	English
Pages	47-48
Number of pages	2
State	Published - 1999
Event	Proceedings of the 1999 Symposium on VLSI Circuits - Kyoto, Jpn Duration: 17 Jun 1999 → 19 Jun 1999

Conference

Conference	Proceedings of the 1999 Symposium on VLSI Circuits
City	Kyoto, Jpn
Period	17/06/99 → 19/06/99

Cite this

@conference{3613a06290d34642b8418daca6afa10a,

title = "1Gbps transceiver with receiver-end deskewing capability using non-uniform tracked oversampling and a 250-750MHz four-phase DLL",

abstract = "This paper describes a low power, 1Gbps, CMOS link with measured bit error rate (BER) < 10-14. To obtain the low BER, skew between clock and data is detected and removed by using non-uniform tracked over-sampling technique with a high-resolution phase control. A delay-locked loop (DLL) with a wide operating frequency range of 250-750MHz generates four phase sampling clocks.",

author = "Yongsam Moon and Jeong, {Deog Kyoon}",

year = "1999",

language = "English",

pages = "47--48",

note = "Proceedings of the 1999 Symposium on VLSI Circuits ; Conference date: 17-06-1999 Through 19-06-1999",

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TY - CONF

T1 - 1Gbps transceiver with receiver-end deskewing capability using non-uniform tracked oversampling and a 250-750MHz four-phase DLL

AU - Moon, Yongsam

AU - Jeong, Deog Kyoon

PY - 1999

Y1 - 1999

N2 - This paper describes a low power, 1Gbps, CMOS link with measured bit error rate (BER) < 10-14. To obtain the low BER, skew between clock and data is detected and removed by using non-uniform tracked over-sampling technique with a high-resolution phase control. A delay-locked loop (DLL) with a wide operating frequency range of 250-750MHz generates four phase sampling clocks.

AB - This paper describes a low power, 1Gbps, CMOS link with measured bit error rate (BER) < 10-14. To obtain the low BER, skew between clock and data is detected and removed by using non-uniform tracked over-sampling technique with a high-resolution phase control. A delay-locked loop (DLL) with a wide operating frequency range of 250-750MHz generates four phase sampling clocks.

UR - http://www.scopus.com/inward/record.url?scp=0033280468&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0033280468

SP - 47

EP - 48

T2 - Proceedings of the 1999 Symposium on VLSI Circuits

Y2 - 17 June 1999 through 19 June 1999

ER -

1Gbps transceiver with receiver-end deskewing capability using non-uniform tracked oversampling and a 250-750MHz four-phase DLL

Abstract

Conference

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