3-D Stacked Synapse Array Based on Charge-Trap Flash Memory for Implementation of Deep Neural Networks

Yu Jeong Park, Hui Tae Kwon, Boram Kim, Won Joo Lee, Dae Hoon Wee, Hyun Seok Choi, Byung Gook Park, Jong Ho Lee, Yoon Kim

Research output: Contribution to journalArticlepeer-review

38 Scopus citations

Abstract

This paper proposes a synaptic device based on charge-trap flash memory that has good CMOS compatibility and superior reliability characteristics compared with other synaptic devices. Using hot-electron injection and hot-hole injection, we designed operation methods to implement gradual conductance modulation and spike-timing-dependent plasticity. We demonstrate the feasibility of the device for neuromorphic applications through both a device-level technology computer-aided design simulation and a system-level MATLAB simulation. For the first time, we also propose a 3-D stacked synapse array and present the structure, operation, and process methods. The proposed array architecture features a small area and low process cost and could be a novel solution for neuromorphic systems for implementing deep neural networks.

Original languageEnglish
Article number8556062
Pages (from-to)420-427
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume66
Issue number1
DOIs
StatePublished - Jan 2019

Keywords

  • 3-D neuromorphic system
  • charge-trap flash (CTF) memory
  • deep neural network (DNN)
  • spike-time-dependent plasticity (STDP)
  • stacked synapse array
  • synapse device

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