32×32-bit adiabatic register file with supply clock generator

Yong Moon, Deog Kyoon Jeong

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations


A 32×32 b adiabatic register file with one read port and one write port is designed. A 4-phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the word line and bit line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are based on ECRL (Efficient Charge Recovery Logic) and are integrated using 0.8 μm CMOS technology. Measurement results show that power consumption of the core is significantly reduced by a factor of up to 3.5 compared with a conventional circuit.

Original languageEnglish
Number of pages2
StatePublished - 1997
EventProceedings of the 1997 Symposium on VLSI Circuits - Kyoto, Jpn
Duration: 12 Jun 199714 Jun 1997


ConferenceProceedings of the 1997 Symposium on VLSI Circuits
CityKyoto, Jpn


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