32×32-bit adiabatic register file with supply clock generator

Yong Moon; Deog Kyoon Jeong

32×32-bit adiabatic register file with supply clock generator

Yong Moon, Deog Kyoon Jeong

School of Electrical and Computer Engineering

Seoul National University

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

A 32×32 b adiabatic register file with one read port and one write port is designed. A 4-phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the word line and bit line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are based on ECRL (Efficient Charge Recovery Logic) and are integrated using 0.8 μm CMOS technology. Measurement results show that power consumption of the core is significantly reduced by a factor of up to 3.5 compared with a conventional circuit.

Original language	English
Pages	27-28
Number of pages	2
State	Published - 1997
Event	Proceedings of the 1997 Symposium on VLSI Circuits - Kyoto, Jpn Duration: 12 Jun 1997 → 14 Jun 1997

Conference

Conference	Proceedings of the 1997 Symposium on VLSI Circuits
City	Kyoto, Jpn
Period	12/06/97 → 14/06/97

Cite this

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title = "32×32-bit adiabatic register file with supply clock generator",

abstract = "A 32×32 b adiabatic register file with one read port and one write port is designed. A 4-phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the word line and bit line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are based on ECRL (Efficient Charge Recovery Logic) and are integrated using 0.8 μm CMOS technology. Measurement results show that power consumption of the core is significantly reduced by a factor of up to 3.5 compared with a conventional circuit.",

author = "Yong Moon and Jeong, {Deog Kyoon}",

year = "1997",

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note = "Proceedings of the 1997 Symposium on VLSI Circuits ; Conference date: 12-06-1997 Through 14-06-1997",

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AU - Moon, Yong

AU - Jeong, Deog Kyoon

PY - 1997

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N2 - A 32×32 b adiabatic register file with one read port and one write port is designed. A 4-phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the word line and bit line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are based on ECRL (Efficient Charge Recovery Logic) and are integrated using 0.8 μm CMOS technology. Measurement results show that power consumption of the core is significantly reduced by a factor of up to 3.5 compared with a conventional circuit.

AB - A 32×32 b adiabatic register file with one read port and one write port is designed. A 4-phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the word line and bit line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are based on ECRL (Efficient Charge Recovery Logic) and are integrated using 0.8 μm CMOS technology. Measurement results show that power consumption of the core is significantly reduced by a factor of up to 3.5 compared with a conventional circuit.

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M3 - Paper

AN - SCOPUS:0031339589

SP - 27

EP - 28

T2 - Proceedings of the 1997 Symposium on VLSI Circuits

Y2 - 12 June 1997 through 14 June 1997

ER -

32×32-bit adiabatic register file with supply clock generator

Abstract

Conference

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