3D technology computer-aided design-based optimization of channel radius considering line edge roughness on gate-all-around nanowire FET

In this work, 3D TCAD-based optimization of channel radius was performed considering line edge roughness (LER) on 5 nm node gate-all-around (GAA) nanowire (NW) FET. As the channel radius is scaled down below 3 nm, we are confronted with seriously reduced driving current due to two major factors where one is small channel carrier density induced by quantum effect (QE) and the other is mobility degradation induced by thickness fluctuation and surface phonon scattering. For the first time, the guideline of channel radius for high performance were studied where the statistical analysis of LER was performed considering QE and thin layer model (TLM) which covers mobility degradation induced by scattering for thin layer.