62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells

Yongsam Moon; Jongsang Choi; Kyeongho Lee; Deog Kyoon Jeong; Min Kyu Kim

62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells

Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog Kyoon Jeong, Min Kyu Kim

School of Electrical and Computer Engineering

Seoul National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper describes a low-jitter multi-phase delay-locked loop (DLL) with a wide operating range of 62.5-250 MHz. A replica delay line attached to the core DLL enables it to fully utilize the frequency range of its voltage-controlled delay line. The DLL incorporates dynamic phase detectors and triply controlled delay cells with duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip is fabricated using a 0.35 μm CMOS process. The measured jitter is suppressed to be less than 44 ps peak-to-peak over the operating frequency range in a noisy environment with other digital circuits activated on the same chip.

Original language	English
Title of host publication	Proceedings of the Custom Integrated Circuits Conference
Publisher	IEEE
Pages	299-302
Number of pages	4
ISBN (Print)	0780354443
State	Published - 1999
Event	Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99 - San Diego, CA, USA Duration: 16 May 1999 → 19 May 1999

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Conference

Conference	Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99
City	San Diego, CA, USA
Period	16/05/99 → 19/05/99

Cite this

@inproceedings{7a96654cdde64ee1aa5e293f4458b5dc,

title = "62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells",

abstract = "This paper describes a low-jitter multi-phase delay-locked loop (DLL) with a wide operating range of 62.5-250 MHz. A replica delay line attached to the core DLL enables it to fully utilize the frequency range of its voltage-controlled delay line. The DLL incorporates dynamic phase detectors and triply controlled delay cells with duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip is fabricated using a 0.35 μm CMOS process. The measured jitter is suppressed to be less than 44 ps peak-to-peak over the operating frequency range in a noisy environment with other digital circuits activated on the same chip.",

author = "Yongsam Moon and Jongsang Choi and Kyeongho Lee and Jeong, {Deog Kyoon} and Kim, {Min Kyu}",

year = "1999",

language = "English",

isbn = "0780354443",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "IEEE",

pages = "299--302",

booktitle = "Proceedings of the Custom Integrated Circuits Conference",

note = "Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99 ; Conference date: 16-05-1999 Through 19-05-1999",

}

Moon, Y, Choi, J, Lee, K, Jeong, DK & Kim, MK 1999, 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. in Proceedings of the Custom Integrated Circuits Conference. Proceedings of the Custom Integrated Circuits Conference, IEEE, pp. 299-302, Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99, San Diego, CA, USA, 16/05/99.

62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. / Moon, Yongsam; Choi, Jongsang; Lee, Kyeongho et al.
Proceedings of the Custom Integrated Circuits Conference. IEEE, 1999. p. 299-302 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells

AU - Moon, Yongsam

AU - Choi, Jongsang

AU - Lee, Kyeongho

AU - Jeong, Deog Kyoon

AU - Kim, Min Kyu

PY - 1999

Y1 - 1999

N2 - This paper describes a low-jitter multi-phase delay-locked loop (DLL) with a wide operating range of 62.5-250 MHz. A replica delay line attached to the core DLL enables it to fully utilize the frequency range of its voltage-controlled delay line. The DLL incorporates dynamic phase detectors and triply controlled delay cells with duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip is fabricated using a 0.35 μm CMOS process. The measured jitter is suppressed to be less than 44 ps peak-to-peak over the operating frequency range in a noisy environment with other digital circuits activated on the same chip.

AB - This paper describes a low-jitter multi-phase delay-locked loop (DLL) with a wide operating range of 62.5-250 MHz. A replica delay line attached to the core DLL enables it to fully utilize the frequency range of its voltage-controlled delay line. The DLL incorporates dynamic phase detectors and triply controlled delay cells with duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip is fabricated using a 0.35 μm CMOS process. The measured jitter is suppressed to be less than 44 ps peak-to-peak over the operating frequency range in a noisy environment with other digital circuits activated on the same chip.

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T3 - Proceedings of the Custom Integrated Circuits Conference

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BT - Proceedings of the Custom Integrated Circuits Conference

PB - IEEE

T2 - Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99

Y2 - 16 May 1999 through 19 May 1999

ER -

62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells

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