960Mbps/pin interface for skew-tolerant bus using low jitter PLL

Sungjoon Kim; Kyeongho Lee; Yongsam Moon; Deog Kyoon Jeong; Yunho Choi; Hyung Kyu Lim

960Mbps/pin interface for skew-tolerant bus using low jitter PLL

Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog Kyoon Jeong, Yunho Choi, Hyung Kyu Lim

School of Electrical and Computer Engineering

Seoul National University

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

This paper describes an I/O scheme for use as a high-speed bus which eliminates setup and hold time requirements between clock and data by using oversampling method. The I/O circuit uses low jitter PLL which suppresses the effect of supply noise. Two Experimental chips with 4 pin interface have been fabricated with 0.6μm CMOS technology, which exhibits the bandwidth of 960Mbps per pin.

Original language	English
Pages	118-119
Number of pages	2
State	Published - 1996
Event	Proceedings of the 1996 Symposium on VLSI Circuits - Honolulu, HI, USA Duration: 13 Jun 1996 → 15 Jun 1996

Conference

Conference	Proceedings of the 1996 Symposium on VLSI Circuits
City	Honolulu, HI, USA
Period	13/06/96 → 15/06/96

Cite this

@conference{270b39e00afb41a88bb3140b76000804,

title = "960Mbps/pin interface for skew-tolerant bus using low jitter PLL",

abstract = "This paper describes an I/O scheme for use as a high-speed bus which eliminates setup and hold time requirements between clock and data by using oversampling method. The I/O circuit uses low jitter PLL which suppresses the effect of supply noise. Two Experimental chips with 4 pin interface have been fabricated with 0.6μm CMOS technology, which exhibits the bandwidth of 960Mbps per pin.",

author = "Sungjoon Kim and Kyeongho Lee and Yongsam Moon and Jeong, {Deog Kyoon} and Yunho Choi and Lim, {Hyung Kyu}",

year = "1996",

language = "English",

pages = "118--119",

note = "Proceedings of the 1996 Symposium on VLSI Circuits ; Conference date: 13-06-1996 Through 15-06-1996",

}

TY - CONF

T1 - 960Mbps/pin interface for skew-tolerant bus using low jitter PLL

AU - Kim, Sungjoon

AU - Lee, Kyeongho

AU - Moon, Yongsam

AU - Jeong, Deog Kyoon

AU - Choi, Yunho

AU - Lim, Hyung Kyu

PY - 1996

Y1 - 1996

N2 - This paper describes an I/O scheme for use as a high-speed bus which eliminates setup and hold time requirements between clock and data by using oversampling method. The I/O circuit uses low jitter PLL which suppresses the effect of supply noise. Two Experimental chips with 4 pin interface have been fabricated with 0.6μm CMOS technology, which exhibits the bandwidth of 960Mbps per pin.

AB - This paper describes an I/O scheme for use as a high-speed bus which eliminates setup and hold time requirements between clock and data by using oversampling method. The I/O circuit uses low jitter PLL which suppresses the effect of supply noise. Two Experimental chips with 4 pin interface have been fabricated with 0.6μm CMOS technology, which exhibits the bandwidth of 960Mbps per pin.

UR - http://www.scopus.com/inward/record.url?scp=0029713707&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0029713707

SP - 118

EP - 119

T2 - Proceedings of the 1996 Symposium on VLSI Circuits

Y2 - 13 June 1996 through 15 June 1996

ER -

960Mbps/pin interface for skew-tolerant bus using low jitter PLL

Abstract

Conference

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