A 0.6-2.5GBaud CMOS tracked 3× oversampling transceiver with dead-zone phase detection for robust clock/data recovery

Y. Moon; D. K. Jeong; G. Ahn

A 0.6-2.5GBaud CMOS tracked 3× oversampling transceiver with dead-zone phase detection for robust clock/data recovery

Y. Moon, D. K. Jeong, G. Ahn

School of Electrical and Computer Engineering

Seoul National University

Research output: Contribution to journal › Conference article › peer-review

9 Scopus citations

Abstract

The transceiver incorporates a voltage-mode driver and an analog multi-phase delay-locked loop (DLL) in the transmitter section for high-bandwidth communication systems. The voltage mode driver with active pull-up and pull-down maintaines speed regardless of cable impedance unlike a conventional current-mode driver. A voltage-controlled delay line (VCDL), consisting of 10 delay cells, generates the same number of clock ouputs. The phase-locked loops should have a structure immune to supply noise and should also contian fewer noise sources for better jitter performance.

Original language	English
Pages (from-to)	212-213+448
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
State	Published - 2001
Event	Digest of Technical Papers - IEEE International Solid-State Circuits Conference - Duration: 5 Feb 2001 → 6 Feb 2001

Cite this

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title = "A 0.6-2.5GBaud CMOS tracked 3× oversampling transceiver with dead-zone phase detection for robust clock/data recovery",

abstract = "The transceiver incorporates a voltage-mode driver and an analog multi-phase delay-locked loop (DLL) in the transmitter section for high-bandwidth communication systems. The voltage mode driver with active pull-up and pull-down maintaines speed regardless of cable impedance unlike a conventional current-mode driver. A voltage-controlled delay line (VCDL), consisting of 10 delay cells, generates the same number of clock ouputs. The phase-locked loops should have a structure immune to supply noise and should also contian fewer noise sources for better jitter performance.",

author = "Y. Moon and Jeong, {D. K.} and G. Ahn",

year = "2001",

language = "English",

pages = "212--213+448",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference ; Conference date: 05-02-2001 Through 06-02-2001",

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T1 - A 0.6-2.5GBaud CMOS tracked 3× oversampling transceiver with dead-zone phase detection for robust clock/data recovery

AU - Moon, Y.

AU - Jeong, D. K.

AU - Ahn, G.

PY - 2001

Y1 - 2001

N2 - The transceiver incorporates a voltage-mode driver and an analog multi-phase delay-locked loop (DLL) in the transmitter section for high-bandwidth communication systems. The voltage mode driver with active pull-up and pull-down maintaines speed regardless of cable impedance unlike a conventional current-mode driver. A voltage-controlled delay line (VCDL), consisting of 10 delay cells, generates the same number of clock ouputs. The phase-locked loops should have a structure immune to supply noise and should also contian fewer noise sources for better jitter performance.

AB - The transceiver incorporates a voltage-mode driver and an analog multi-phase delay-locked loop (DLL) in the transmitter section for high-bandwidth communication systems. The voltage mode driver with active pull-up and pull-down maintaines speed regardless of cable impedance unlike a conventional current-mode driver. A voltage-controlled delay line (VCDL), consisting of 10 delay cells, generates the same number of clock ouputs. The phase-locked loops should have a structure immune to supply noise and should also contian fewer noise sources for better jitter performance.

UR - http://www.scopus.com/inward/record.url?scp=0035054799&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0035054799

SN - 0193-6530

SP - 212-213+448

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Y2 - 5 February 2001 through 6 February 2001

ER -

A 0.6-2.5GBaud CMOS tracked 3× oversampling transceiver with dead-zone phase detection for robust clock/data recovery

Abstract

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