A 10.2-ghz lc-vco for a 28-nm cmos transmitter with nearest vco-curve selection algorithm

This paper describes an 8.48-to-11.13 GHz LC-VCO for a 28-nm CMOS transmitter. For the discrete tuning of the LC-VCO, a nearest VCO-curve selection algorithm is proposed, which exhibits additional 1-bit resolution. The proposed algorithm even with the LSB of the capacitor-bank control signal being removed shows the same level of quantization error as the conventional algorithm. The PLL fabricated in a 28-nm CMOS process occupies 0.14 mm². The transmitted PLL clock has a phase noise of −94.21 dBc/Hz at 100-kHz offset and the jitter of 815-fs RMS can be obtained by de-embedding the jitter of the reference clock. The PLL and the driver have power consumption of 3 mW and 23 mW respectively with a 1-V supply at 10.2-GHz LC-VCO frequency.