A 18.5 nW 12-bit 1-kS/s Reset-energy saving sar ADC for bio-signal acquisition in 0.18-μ m CMOS

This paper presents three low-power design techniques for successive approximation registers (SAR) analog-to-digital converter (ADC) for bio-potential signal acquisition: Skip-reset, delta (Δ) readout with MSB-rounding, and tri-level split monotonic switching. The skip-reset scheme reduces not only reference energy but also digital switching energy for the ADC reset. The Δ-readout process with the proposed MSB-rounding technique shifts the location of the resolvable range using the previous digital code to increase the hit-rate. Finally, the tri-level split monotonic switching scheme minimizes the CDAC switching activity in predictive residue generation for the Δ-readout process. A prototype ADC was fabricated in a 0.18-μ m CMOS technology and occupies an active area of 0.17 mm². At a 1.5-V supply voltage and a 1-kS/s sampling-rate with the electrocardiogram signal input, the ADC power consumption could be reduced to 18.5 nW, corresponding to 71% power saving, and owing to the proposed techniques from a conventional SAR ADC consuming 63.5 nW.