A 2-bit recessed channel nonvolatile memory device with a lifted charge-trapping node

Jang Gn Yun; Il Han Park; Seongjae Cho; Jung Hoon Lee; Doo Hyun Kim; Gil Sung Lee; Yoon Kim; Jong Duk Lee; Byung Gook Park

doi:10.1109/TNANO.2008.2006049

A 2-bit recessed channel nonvolatile memory device with a lifted charge-trapping node

Jang Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung Gook Park

School of Electrical and Computer Engineering

Seoul National University

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

A novel 2-bit recessed channel nonvolatile memory device is proposed in this paper. Physically separated two charge-trapping nodes are lifted up to achieve large sensing margin in highly scaled memory devices. A successful 2-bit/cell operation with effective suppression of second bit effect is achieved by adopting the lifted charge-trapping node scheme. In addition, the effect of the source/drain junction depth on memory operation characteristics is investigated.

Original language	English
Article number	4633648
Pages (from-to)	111-115
Number of pages	5
Journal	IEEE Transactions on Nanotechnology
Volume	8
Issue number	1
DOIs	https://doi.org/10.1109/TNANO.2008.2006049
State	Published - Jan 2009

Keywords

2-bit nonvolatile memory device
Lifted charge-trapping node scheme
Recessed channel structure
Second bit effect (SBE)

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10.1109/TNANO.2008.2006049

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title = "A 2-bit recessed channel nonvolatile memory device with a lifted charge-trapping node",

abstract = "A novel 2-bit recessed channel nonvolatile memory device is proposed in this paper. Physically separated two charge-trapping nodes are lifted up to achieve large sensing margin in highly scaled memory devices. A successful 2-bit/cell operation with effective suppression of second bit effect is achieved by adopting the lifted charge-trapping node scheme. In addition, the effect of the source/drain junction depth on memory operation characteristics is investigated.",

keywords = "2-bit nonvolatile memory device, Lifted charge-trapping node scheme, Recessed channel structure, Second bit effect (SBE)",

author = "Yun, \{Jang Gn\} and Park, \{Il Han\} and Seongjae Cho and Lee, \{Jung Hoon\} and Kim, \{Doo Hyun\} and Lee, \{Gil Sung\} and Yoon Kim and Lee, \{Jong Duk\} and Park, \{Byung Gook\}",

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AU - Yun, Jang Gn

AU - Park, Il Han

AU - Cho, Seongjae

AU - Lee, Jung Hoon

AU - Kim, Doo Hyun

AU - Lee, Gil Sung

AU - Kim, Yoon

AU - Lee, Jong Duk

AU - Park, Byung Gook

PY - 2009/1

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N2 - A novel 2-bit recessed channel nonvolatile memory device is proposed in this paper. Physically separated two charge-trapping nodes are lifted up to achieve large sensing margin in highly scaled memory devices. A successful 2-bit/cell operation with effective suppression of second bit effect is achieved by adopting the lifted charge-trapping node scheme. In addition, the effect of the source/drain junction depth on memory operation characteristics is investigated.

AB - A novel 2-bit recessed channel nonvolatile memory device is proposed in this paper. Physically separated two charge-trapping nodes are lifted up to achieve large sensing margin in highly scaled memory devices. A successful 2-bit/cell operation with effective suppression of second bit effect is achieved by adopting the lifted charge-trapping node scheme. In addition, the effect of the source/drain junction depth on memory operation characteristics is investigated.

KW - 2-bit nonvolatile memory device

KW - Lifted charge-trapping node scheme

KW - Recessed channel structure

KW - Second bit effect (SBE)

UR - https://www.scopus.com/pages/publications/59049100229

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JO - IEEE Transactions on Nanotechnology

JF - IEEE Transactions on Nanotechnology

IS - 1

M1 - 4633648

ER -

A 2-bit recessed channel nonvolatile memory device with a lifted charge-trapping node

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Keywords

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