A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology

Min Suk Koo; Hakchul Jung; Ickhyun Song; Hee Sauk Jhon; Hyungcheol Shin

doi:10.1109/ICSICT.2008.4734828

A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology

Min Suk Koo, Hakchul Jung, Ickhyun Song, Hee Sauk Jhon, Hyungcheol Shin

School of Advanced Fusion Studies

Seoul National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, design approach of 2.4 GHz CMOS ultra low power Low Noise Amplifier (LNA) using 65 nm CMOS technology is presented. Conventional Inducti -vely degenerated cascode topology where both MOS transistors are biased in sub-threshold region is used. There are many performance factors of LNAs such as signal power gain, noise factor, input referred 1-dB compression point (P _-1 dBin) and power consumption. In low power design, above all things proper power gain and low power consumption should be attained. This limitation makes ultra low power LNA optimization different from ordinary one. We analyze each performance factor in low power design and optimize figure of merit (FoM) with some specification goal.

Original language	English
Title of host publication	ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings
Pages	1488-1491
Number of pages	4
DOIs	https://doi.org/10.1109/ICSICT.2008.4734828
State	Published - 2008
Event	2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 - Beijing, China Duration: 20 Oct 2008 → 23 Oct 2008

Publication series

Name	International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Conference

Conference	2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008
Country/Territory	China
City	Beijing
Period	20/10/08 → 23/10/08

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10.1109/ICSICT.2008.4734828

Cite this

Koo, M. S., Jung, H., Song, I., Jhon, H. S., & Shin, H. (2008). A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology. In ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings (pp. 1488-1491). Article 4734828 (International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT). https://doi.org/10.1109/ICSICT.2008.4734828

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title = "A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology",

abstract = "In this paper, design approach of 2.4 GHz CMOS ultra low power Low Noise Amplifier (LNA) using 65 nm CMOS technology is presented. Conventional Inducti -vely degenerated cascode topology where both MOS transistors are biased in sub-threshold region is used. There are many performance factors of LNAs such as signal power gain, noise factor, input referred 1-dB compression point (P -1 dBin) and power consumption. In low power design, above all things proper power gain and low power consumption should be attained. This limitation makes ultra low power LNA optimization different from ordinary one. We analyze each performance factor in low power design and optimize figure of merit (FoM) with some specification goal.",

author = "Koo, {Min Suk} and Hakchul Jung and Ickhyun Song and Jhon, {Hee Sauk} and Hyungcheol Shin",

year = "2008",

doi = "10.1109/ICSICT.2008.4734828",

language = "English",

isbn = "9781424421855",

series = "International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT",

pages = "1488--1491",

booktitle = "ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings",

note = "2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 ; Conference date: 20-10-2008 Through 23-10-2008",

}

Koo, MS, Jung, H, Song, I, Jhon, HS & Shin, H 2008, A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology. in ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings., 4734828, International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT, pp. 1488-1491, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008, Beijing, China, 20/10/08. https://doi.org/10.1109/ICSICT.2008.4734828

A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology. / Koo, Min Suk; Jung, Hakchul; Song, Ickhyun et al.
ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings. 2008. p. 1488-1491 4734828 (International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - In this paper, design approach of 2.4 GHz CMOS ultra low power Low Noise Amplifier (LNA) using 65 nm CMOS technology is presented. Conventional Inducti -vely degenerated cascode topology where both MOS transistors are biased in sub-threshold region is used. There are many performance factors of LNAs such as signal power gain, noise factor, input referred 1-dB compression point (P -1 dBin) and power consumption. In low power design, above all things proper power gain and low power consumption should be attained. This limitation makes ultra low power LNA optimization different from ordinary one. We analyze each performance factor in low power design and optimize figure of merit (FoM) with some specification goal.

AB - In this paper, design approach of 2.4 GHz CMOS ultra low power Low Noise Amplifier (LNA) using 65 nm CMOS technology is presented. Conventional Inducti -vely degenerated cascode topology where both MOS transistors are biased in sub-threshold region is used. There are many performance factors of LNAs such as signal power gain, noise factor, input referred 1-dB compression point (P -1 dBin) and power consumption. In low power design, above all things proper power gain and low power consumption should be attained. This limitation makes ultra low power LNA optimization different from ordinary one. We analyze each performance factor in low power design and optimize figure of merit (FoM) with some specification goal.

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Koo MS, Jung H, Song I, Jhon HS, Shin H. A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology. In ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings. 2008. p. 1488-1491. 4734828. (International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT). doi: 10.1109/ICSICT.2008.4734828

A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology

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