A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology

Jungwook Yang; Joongho Choi; Daniel M. Kuchta; Kevin G. Stawiasz; Petar Pepeljugoski; H. A. Ainspan

doi:10.1109/4.735704

A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology

Jungwook Yang, Joongho Choi, Daniel M. Kuchta, Kevin G. Stawiasz, Petar Pepeljugoski, H. A. Ainspan

School of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

A 20-channel parallel optical receiver has been developed that achieves the data transfer rate of 1 GByte/s. Each channel takes a dc-coupled optical input and can be driven by a 250 MHz clock to have a data rate of 500 Mb/s/channel. This parallel optical receiver IC is an integral part of a low cost optical bus technology which was demonstrated to be cost competitive with copper interconnect technology. The power supply is 3.3 V to be compatible with system supply. The control inputs are CMOS logic compatible and data outputs are compatible with IEEE low-voltage differential signals. The chip has been fabricated in a 1.2 μm GaAs MESFET technology.

Original language	English
Pages (from-to)	2197-2204
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	33
Issue number	12
DOIs	https://doi.org/10.1109/4.735704
State	Published - Dec 1998

Keywords

Integrated optoelectronics
MESFET's
Optical receivers
Photodetectors

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10.1109/4.735704

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@article{026212741a684d0aa6bebc1d81fb9313,

title = "A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology",

abstract = "A 20-channel parallel optical receiver has been developed that achieves the data transfer rate of 1 GByte/s. Each channel takes a dc-coupled optical input and can be driven by a 250 MHz clock to have a data rate of 500 Mb/s/channel. This parallel optical receiver IC is an integral part of a low cost optical bus technology which was demonstrated to be cost competitive with copper interconnect technology. The power supply is 3.3 V to be compatible with system supply. The control inputs are CMOS logic compatible and data outputs are compatible with IEEE low-voltage differential signals. The chip has been fabricated in a 1.2 μm GaAs MESFET technology.",

keywords = "Integrated optoelectronics, MESFET's, Optical receivers, Photodetectors",

author = "Jungwook Yang and Joongho Choi and Kuchta, \{Daniel M.\} and Stawiasz, \{Kevin G.\} and Petar Pepeljugoski and Ainspan, \{H. A.\}",

year = "1998",

month = dec,

doi = "10.1109/4.735704",

language = "English",

volume = "33",

pages = "2197--2204",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "12",

}

TY - JOUR

T1 - A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology

AU - Yang, Jungwook

AU - Choi, Joongho

AU - Kuchta, Daniel M.

AU - Stawiasz, Kevin G.

AU - Pepeljugoski, Petar

AU - Ainspan, H. A.

PY - 1998/12

Y1 - 1998/12

N2 - A 20-channel parallel optical receiver has been developed that achieves the data transfer rate of 1 GByte/s. Each channel takes a dc-coupled optical input and can be driven by a 250 MHz clock to have a data rate of 500 Mb/s/channel. This parallel optical receiver IC is an integral part of a low cost optical bus technology which was demonstrated to be cost competitive with copper interconnect technology. The power supply is 3.3 V to be compatible with system supply. The control inputs are CMOS logic compatible and data outputs are compatible with IEEE low-voltage differential signals. The chip has been fabricated in a 1.2 μm GaAs MESFET technology.

AB - A 20-channel parallel optical receiver has been developed that achieves the data transfer rate of 1 GByte/s. Each channel takes a dc-coupled optical input and can be driven by a 250 MHz clock to have a data rate of 500 Mb/s/channel. This parallel optical receiver IC is an integral part of a low cost optical bus technology which was demonstrated to be cost competitive with copper interconnect technology. The power supply is 3.3 V to be compatible with system supply. The control inputs are CMOS logic compatible and data outputs are compatible with IEEE low-voltage differential signals. The chip has been fabricated in a 1.2 μm GaAs MESFET technology.

KW - Integrated optoelectronics

KW - MESFET's

KW - Optical receivers

KW - Photodetectors

UR - https://www.scopus.com/pages/publications/0032308787

U2 - 10.1109/4.735704

DO - 10.1109/4.735704

M3 - Article

AN - SCOPUS:0032308787

SN - 0018-9200

VL - 33

SP - 2197

EP - 2204

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 12

ER -

A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology

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Keywords

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