TY - GEN
T1 - A 3.3-V analog front-end chip for HomePNA applications
AU - Shin, Jaeyoung
AU - Choi, Joongho
AU - Lim, Jinup
AU - Noh, Sungwon
AU - Baek, Namil
AU - Lee, Jong Hyeong
PY - 2001
Y1 - 2001
N2 - In this paper, we designed the analog front-end chip for HomePNA (Home Phoneline Networking Alliance) physical layer applications. The chip mainly consists of the transmitter (Tx) path and receiver (Rx) path. The transmitter path includes the pulse generation block, Tx filter, programmable gain amplifier, and line driver. The receiver path includes the input buffer, automatic gain control amplifier, Rx filter, and slicing circuit with variable threshold level. The chip is fabricated in a 0.35-/spl mu/m CMOS technology and consumes power dissipation of 150 mW at a 3.3-V supply voltage.
AB - In this paper, we designed the analog front-end chip for HomePNA (Home Phoneline Networking Alliance) physical layer applications. The chip mainly consists of the transmitter (Tx) path and receiver (Rx) path. The transmitter path includes the pulse generation block, Tx filter, programmable gain amplifier, and line driver. The receiver path includes the input buffer, automatic gain control amplifier, Rx filter, and slicing circuit with variable threshold level. The chip is fabricated in a 0.35-/spl mu/m CMOS technology and consumes power dissipation of 150 mW at a 3.3-V supply voltage.
UR - http://www.scopus.com/inward/record.url?scp=84878619531&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2001.922333
DO - 10.1109/ISCAS.2001.922333
M3 - Conference contribution
AN - SCOPUS:84878619531
SN - 0780366859
SN - 9780780366855
T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
SP - 698
EP - 701
BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Y2 - 6 May 2001 through 9 May 2001
ER -