A 3.3-V analog front-end chip for HomePNA applications

J. Shin; J. Choi; J. Lim; S. Noh; N. Baek; J. H. Lee

A 3.3-V analog front-end chip for HomePNA applications

J. Shin, J. Choi, J. Lim, S. Noh, N. Baek, J. H. Lee

University of Seoul

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this paper, we designed the analog front-end chip for HomePNA (Home Phoneline Networking Alliance) physical layer applications. The chip mainly consists of the transmitter (Tx) path and receiver (Rx) path. The transmitter path includes the pulse generation block, Tx filter, programmable gain amplifier, and line driver. The receiver path includes the input buffer, automatic gain control amplifier, Rx filter, and slicing circuit with variable threshold level. The chip is fabricated in a 0.35-μm CMOS technology and consumes power dissipation of 150mW at a 3.3-V supply voltage.

Original language	English
Pages (from-to)	IV698-IV701
Journal	Materials Research Society Symposium - Proceedings
Volume	626
State	Published - 2001
Event	Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States Duration: 24 Apr 2000 → 27 Apr 2000

Cite this

@article{ed3ef027554645958aa18644f2c704e3,

title = "A 3.3-V analog front-end chip for HomePNA applications",

abstract = "In this paper, we designed the analog front-end chip for HomePNA (Home Phoneline Networking Alliance) physical layer applications. The chip mainly consists of the transmitter (Tx) path and receiver (Rx) path. The transmitter path includes the pulse generation block, Tx filter, programmable gain amplifier, and line driver. The receiver path includes the input buffer, automatic gain control amplifier, Rx filter, and slicing circuit with variable threshold level. The chip is fabricated in a 0.35-μm CMOS technology and consumes power dissipation of 150mW at a 3.3-V supply voltage.",

author = "J. Shin and J. Choi and J. Lim and S. Noh and N. Baek and Lee, {J. H.}",

year = "2001",

language = "English",

volume = "626",

pages = "IV698--IV701",

journal = "Materials Research Society Symposium - Proceedings",

issn = "0272-9172",

publisher = "Materials Research Society",

note = "Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications ; Conference date: 24-04-2000 Through 27-04-2000",

}

TY - JOUR

T1 - A 3.3-V analog front-end chip for HomePNA applications

AU - Shin, J.

AU - Choi, J.

AU - Lim, J.

AU - Noh, S.

AU - Baek, N.

AU - Lee, J. H.

PY - 2001

Y1 - 2001

N2 - In this paper, we designed the analog front-end chip for HomePNA (Home Phoneline Networking Alliance) physical layer applications. The chip mainly consists of the transmitter (Tx) path and receiver (Rx) path. The transmitter path includes the pulse generation block, Tx filter, programmable gain amplifier, and line driver. The receiver path includes the input buffer, automatic gain control amplifier, Rx filter, and slicing circuit with variable threshold level. The chip is fabricated in a 0.35-μm CMOS technology and consumes power dissipation of 150mW at a 3.3-V supply voltage.

AB - In this paper, we designed the analog front-end chip for HomePNA (Home Phoneline Networking Alliance) physical layer applications. The chip mainly consists of the transmitter (Tx) path and receiver (Rx) path. The transmitter path includes the pulse generation block, Tx filter, programmable gain amplifier, and line driver. The receiver path includes the input buffer, automatic gain control amplifier, Rx filter, and slicing circuit with variable threshold level. The chip is fabricated in a 0.35-μm CMOS technology and consumes power dissipation of 150mW at a 3.3-V supply voltage.

UR - http://www.scopus.com/inward/record.url?scp=17044458926&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:17044458926

SN - 0272-9172

VL - 626

SP - IV698-IV701

JO - Materials Research Society Symposium - Proceedings

JF - Materials Research Society Symposium - Proceedings

T2 - Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications

Y2 - 24 April 2000 through 27 April 2000

ER -

A 3.3-V analog front-end chip for HomePNA applications

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