A 3.3-V analog front-end chip for HomePNA applications

J. Shin, J. Choi, J. Lim, S. Noh, N. Baek, J. H. Lee

Research output: Contribution to journalConference articlepeer-review


In this paper, we designed the analog front-end chip for HomePNA (Home Phoneline Networking Alliance) physical layer applications. The chip mainly consists of the transmitter (Tx) path and receiver (Rx) path. The transmitter path includes the pulse generation block, Tx filter, programmable gain amplifier, and line driver. The receiver path includes the input buffer, automatic gain control amplifier, Rx filter, and slicing circuit with variable threshold level. The chip is fabricated in a 0.35-μm CMOS technology and consumes power dissipation of 150mW at a 3.3-V supply voltage.

Original languageEnglish
Pages (from-to)IV698-IV701
JournalMaterials Research Society Symposium - Proceedings
StatePublished - 2001
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 24 Apr 200027 Apr 2000


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