A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC

Min Jae Seo; Ye Dam Kim; Jae Hyun Chung; Seung Tak Ryu

doi:10.23919/VLSIC.2019.8778005

A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC

Min Jae Seo, Ye Dam Kim, Jae Hyun Chung, Seung Tak Ryu

School of Advanced Fusion Studies

Korea Advanced Institute of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

20 Scopus citations

Abstract

This work proposes a dual-residue pipelined-SAR ADC that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fabricated in a 40nm CMOS occupies an active area of 0.026 mm² and achieves an SNDR of 62.1 dB at Nyquist and 67.1 dB SFDR under a 0.9 V supply.

Original language	English
Title of host publication	2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C72-C73
ISBN (Electronic)	9784863487185
DOIs	https://doi.org/10.23919/VLSIC.2019.8778005
State	Published - Jun 2019
Event	33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan Duration: 9 Jun 2019 → 14 Jun 2019

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2019-June

Conference

Conference	33rd Symposium on VLSI Circuits, VLSI Circuits 2019
Country/Territory	Japan
City	Kyoto
Period	9/06/19 → 14/06/19

Access to Document

10.23919/VLSIC.2019.8778005

Cite this

Seo, M. J., Kim, Y. D., Chung, J. H., & Ryu, S. T. (2019). A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers (pp. C72-C73). Article 8778005 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2019.8778005

@inproceedings{70351842df1944e38c45854afc23ad0c,

title = "A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC",

abstract = "This work proposes a dual-residue pipelined-SAR ADC that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fabricated in a 40nm CMOS occupies an active area of 0.026 mm2 and achieves an SNDR of 62.1 dB at Nyquist and 67.1 dB SFDR under a 0.9 V supply.",

author = "Seo, {Min Jae} and Kim, {Ye Dam} and Chung, {Jae Hyun} and Ryu, {Seung Tak}",

note = "Publisher Copyright: {\textcopyright} 2019 JSAP.; 33rd Symposium on VLSI Circuits, VLSI Circuits 2019 ; Conference date: 09-06-2019 Through 14-06-2019",

year = "2019",

month = jun,

doi = "10.23919/VLSIC.2019.8778005",

language = "English",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "C72--C73",

booktitle = "2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers",

address = "United States",

}

Seo, MJ, Kim, YD, Chung, JH & Ryu, ST 2019, A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC. in 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers., 8778005, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. C72-C73, 33rd Symposium on VLSI Circuits, VLSI Circuits 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIC.2019.8778005

A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC. / Seo, Min Jae; Kim, Ye Dam; Chung, Jae Hyun et al.
2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. C72-C73 8778005 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC

AU - Seo, Min Jae

AU - Kim, Ye Dam

AU - Chung, Jae Hyun

AU - Ryu, Seung Tak

PY - 2019/6

Y1 - 2019/6

N2 - This work proposes a dual-residue pipelined-SAR ADC that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fabricated in a 40nm CMOS occupies an active area of 0.026 mm2 and achieves an SNDR of 62.1 dB at Nyquist and 67.1 dB SFDR under a 0.9 V supply.

AB - This work proposes a dual-residue pipelined-SAR ADC that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fabricated in a 40nm CMOS occupies an active area of 0.026 mm2 and achieves an SNDR of 62.1 dB at Nyquist and 67.1 dB SFDR under a 0.9 V supply.

UR - http://www.scopus.com/inward/record.url?scp=85073914809&partnerID=8YFLogxK

U2 - 10.23919/VLSIC.2019.8778005

DO - 10.23919/VLSIC.2019.8778005

M3 - Conference contribution

AN - SCOPUS:85073914809

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - C72-C73

BT - 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 33rd Symposium on VLSI Circuits, VLSI Circuits 2019

Y2 - 9 June 2019 through 14 June 2019

ER -

A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this