@inproceedings{70351842df1944e38c45854afc23ad0c,
title = "A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC",
abstract = "This work proposes a dual-residue pipelined-SAR ADC that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fabricated in a 40nm CMOS occupies an active area of 0.026 mm2 and achieves an SNDR of 62.1 dB at Nyquist and 67.1 dB SFDR under a 0.9 V supply.",
author = "Seo, \{Min Jae\} and Kim, \{Ye Dam\} and Chung, \{Jae Hyun\} and Ryu, \{Seung Tak\}",
note = "Publisher Copyright: {\textcopyright} 2019 JSAP.; 33rd Symposium on VLSI Circuits, VLSI Circuits 2019 ; Conference date: 09-06-2019 Through 14-06-2019",
year = "2019",
month = jun,
doi = "10.23919/VLSIC.2019.8778005",
language = "English",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "C72--C73",
booktitle = "2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers",
address = "United States",
}