A 4.2mW 10MHz BW 74.4dB SNDR fourth-order CT DSM with second-order digital noise coupling utilizing an 8b SAR ADC

Il Hoon Jang, Min Jae Seo, Mi Young Kim, Jae Keun Lee, Seung Yeob Baek, Sun Woo Kwon, Michael Choi, Hyung Jong Ko, Seung Tak Ryu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

15 Scopus citations

Abstract

A compact and low-power digital-domain noise coupling technique is proposed for higher-order CT DSM implementation, exploiting the architectural advantage of a SAR ADC and a simple digital filter. With an 8b SAR ADC and a second-order digital noise coupling filter, a prototype fourth-order DSM achieves 74.4dB SNDR for 10MHz BW with an OSR of 16 in a 28nm CMOS, showing an FoMs-dr of 174.5dB.

Original languageEnglish
Title of host publication2017 Symposium on VLSI Circuits, VLSI Circuits 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC34-C35
ISBN (Electronic)9784863486065
DOIs
StatePublished - 10 Aug 2017
Event31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan
Duration: 5 Jun 20178 Jun 2017

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference31st Symposium on VLSI Circuits, VLSI Circuits 2017
Country/TerritoryJapan
CityKyoto
Period5/06/178/06/17

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