A 45nm 4Gb 3-dimensional double-slacked multi-level NAND flash memory with shared bitline structure

Ki Tae Park; Doogon Kim; Soonwook Hwang; Myounggon Kang; Hoosung Cho; Youngwook Jeong; Yong Il Seo; Jaehoon Jang; Han Soo Kim; Soon Moon Jung; Yeong Taek Lee; Changhyun Kim; Won Seong Lee

doi:10.1109/ISSCC.2008.4523281

A 45nm 4Gb 3-dimensional double-slacked multi-level NAND flash memory with shared bitline structure

Ki Tae Park
, Doogon Kim
, Soonwook Hwang
, Myounggon Kang
, Hoosung Cho
, Youngwook Jeong
, Yong Il Seo
, Jaehoon Jang
, Han Soo Kim
, Soon Moon Jung
, Yeong Taek Lee
, Changhyun Kim
, Won Seong Lee

School of Advanced Fusion Studies

Samsung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

35 Scopus citations

Abstract

A 4Gb 3D double-stacked multi-level-cell NAND flash memory is developed using 45nm floating-gate CMOS with single-crystal-Si layer stacking. The 3D device stacks two Si layers that each contain 2Gb memory arrays with a cell size of 0.0021 μm²/b per unit feature area. A fully 3D architecture achieves 2.5MB/s with 2kB page size and 40μs read-access time, which are almost equivalent to conventional planar devices.

Original language	English
Title of host publication	2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	509-511
Number of pages	3
ISBN (Print)	9781424420100
DOIs	https://doi.org/10.1109/ISSCC.2008.4523281
State	Published - 2008
Event	2008 IEEE International Solid State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 3 Feb 2008 → 7 Feb 2008

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	51
ISSN (Print)	0193-6530

Conference

Conference	2008 IEEE International Solid State Circuits Conference, ISSCC
Country/Territory	United States
City	San Francisco, CA
Period	3/02/08 → 7/02/08

Access to Document

10.1109/ISSCC.2008.4523281

Cite this

Park, K. T., Kim, D., Hwang, S., Kang, M., Cho, H., Jeong, Y., Seo, Y. I., Jang, J., Kim, H. S., Jung, S. M., Lee, Y. T., Kim, C., & Lee, W. S. (2008). A 45nm 4Gb 3-dimensional double-slacked multi-level NAND flash memory with shared bitline structure. In 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC (pp. 509-511). Article 4523281 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2008.4523281

Park, Ki Tae ; Kim, Doogon ; Hwang, Soonwook et al. / A 45nm 4Gb 3-dimensional double-slacked multi-level NAND flash memory with shared bitline structure. 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. Institute of Electrical and Electronics Engineers Inc., 2008. pp. 509-511 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{67f9db4f72b64388b6e9ced8c72dd3b0,

title = "A 45nm 4Gb 3-dimensional double-slacked multi-level NAND flash memory with shared bitline structure",

abstract = "A 4Gb 3D double-stacked multi-level-cell NAND flash memory is developed using 45nm floating-gate CMOS with single-crystal-Si layer stacking. The 3D device stacks two Si layers that each contain 2Gb memory arrays with a cell size of 0.0021 μm2/b per unit feature area. A fully 3D architecture achieves 2.5MB/s with 2kB page size and 40μs read-access time, which are almost equivalent to conventional planar devices.",

author = "Park, \{Ki Tae\} and Doogon Kim and Soonwook Hwang and Myounggon Kang and Hoosung Cho and Youngwook Jeong and Seo, \{Yong Il\} and Jaehoon Jang and Kim, \{Han Soo\} and Jung, \{Soon Moon\} and Lee, \{Yeong Taek\} and Changhyun Kim and Lee, \{Won Seong\}",

year = "2008",

doi = "10.1109/ISSCC.2008.4523281",

language = "English",

isbn = "9781424420100",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "509--511",

booktitle = "2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC",

address = "United States",

note = "2008 IEEE International Solid State Circuits Conference, ISSCC ; Conference date: 03-02-2008 Through 07-02-2008",

}

Park, KT, Kim, D, Hwang, S, Kang, M, Cho, H, Jeong, Y, Seo, YI, Jang, J, Kim, HS, Jung, SM, Lee, YT, Kim, C & Lee, WS 2008, A 45nm 4Gb 3-dimensional double-slacked multi-level NAND flash memory with shared bitline structure. in 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC., 4523281, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 51, Institute of Electrical and Electronics Engineers Inc., pp. 509-511, 2008 IEEE International Solid State Circuits Conference, ISSCC, San Francisco, CA, United States, 3/02/08. https://doi.org/10.1109/ISSCC.2008.4523281

A 45nm 4Gb 3-dimensional double-slacked multi-level NAND flash memory with shared bitline structure. / Park, Ki Tae; Kim, Doogon; Hwang, Soonwook et al.
2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. Institute of Electrical and Electronics Engineers Inc., 2008. p. 509-511 4523281 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 45nm 4Gb 3-dimensional double-slacked multi-level NAND flash memory with shared bitline structure

AU - Park, Ki Tae

AU - Kim, Doogon

AU - Hwang, Soonwook

AU - Kang, Myounggon

AU - Cho, Hoosung

AU - Jeong, Youngwook

AU - Seo, Yong Il

AU - Jang, Jaehoon

AU - Kim, Han Soo

AU - Jung, Soon Moon

AU - Lee, Yeong Taek

AU - Kim, Changhyun

AU - Lee, Won Seong

PY - 2008

Y1 - 2008

N2 - A 4Gb 3D double-stacked multi-level-cell NAND flash memory is developed using 45nm floating-gate CMOS with single-crystal-Si layer stacking. The 3D device stacks two Si layers that each contain 2Gb memory arrays with a cell size of 0.0021 μm2/b per unit feature area. A fully 3D architecture achieves 2.5MB/s with 2kB page size and 40μs read-access time, which are almost equivalent to conventional planar devices.

AB - A 4Gb 3D double-stacked multi-level-cell NAND flash memory is developed using 45nm floating-gate CMOS with single-crystal-Si layer stacking. The 3D device stacks two Si layers that each contain 2Gb memory arrays with a cell size of 0.0021 μm2/b per unit feature area. A fully 3D architecture achieves 2.5MB/s with 2kB page size and 40μs read-access time, which are almost equivalent to conventional planar devices.

UR - https://www.scopus.com/pages/publications/49549094516

U2 - 10.1109/ISSCC.2008.4523281

DO - 10.1109/ISSCC.2008.4523281

M3 - Conference contribution

AN - SCOPUS:49549094516

SN - 9781424420100

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 509

EP - 511

BT - 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2008 IEEE International Solid State Circuits Conference, ISSCC

Y2 - 3 February 2008 through 7 February 2008

ER -

Park KT, Kim D, Hwang S, Kang M, Cho H, Jeong Y et al. A 45nm 4Gb 3-dimensional double-slacked multi-level NAND flash memory with shared bitline structure. In 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. Institute of Electrical and Electronics Engineers Inc. 2008. p. 509-511. 4523281. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2008.4523281

A 45nm 4Gb 3-dimensional double-slacked multi-level NAND flash memory with shared bitline structure

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this