A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Sang Hyun Lee; Moon Sang Hwang; Youngdon Choi; Sungjoon Kim; Yongsam Moon; Bong Joon Lee; Deog Kyoon Jeong; Wonchan Kim; Young June Park; Gijung Ahn

doi:10.1109/JSSC.2002.804342

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Sang Hyun Lee, Moon Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong Joon Lee, Deog Kyoon Jeong, Wonchan Kim, Young June Park, Gijung Ahn

School of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

53 Scopus citations

Abstract

This paper describes a clock/data recovery circuit (CDR) incorporating a variable-interval 3×-oversampling method for enhanced high-frequency jitter tolerance. The CDR traces the eye-opening region to place the data-sampling clock exactly at the center of data eye, responding to the shape and magnitude of jitter. A sampler with a pair of input-holding switches enables high-speed data sampling with reduced dynamic offset voltage. From the Linearized model of the phase detector, the loop dynamics of the CDR is analyzed. Integrated in a single-chip transceiver with 0.25-μm CMOS technology, the CDR operates at a data rate of 5 Gb/s. The CDR shows a bit error rate of less than 10^-13 when the magnitude of data jitter reaches 60.5% of a bit time.

Original language	English
Pages (from-to)	1822-1830
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	37
Issue number	12
DOIs	https://doi.org/10.1109/JSSC.2002.804342
State	Published - Dec 2002

Keywords

Clock/data recovery
Data eye
Deterministic jitter
High-frequency jitter tolerance
Phase detector
Sampler
Serial link
Variable-interval oversampling

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10.1109/JSSC.2002.804342

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title = "A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit",

abstract = "This paper describes a clock/data recovery circuit (CDR) incorporating a variable-interval 3×-oversampling method for enhanced high-frequency jitter tolerance. The CDR traces the eye-opening region to place the data-sampling clock exactly at the center of data eye, responding to the shape and magnitude of jitter. A sampler with a pair of input-holding switches enables high-speed data sampling with reduced dynamic offset voltage. From the Linearized model of the phase detector, the loop dynamics of the CDR is analyzed. Integrated in a single-chip transceiver with 0.25-μm CMOS technology, the CDR operates at a data rate of 5 Gb/s. The CDR shows a bit error rate of less than 10-13 when the magnitude of data jitter reaches 60.5% of a bit time.",

keywords = "Clock/data recovery, Data eye, Deterministic jitter, High-frequency jitter tolerance, Phase detector, Sampler, Serial link, Variable-interval oversampling",

author = "Lee, {Sang Hyun} and Hwang, {Moon Sang} and Youngdon Choi and Sungjoon Kim and Yongsam Moon and Lee, {Bong Joon} and Jeong, {Deog Kyoon} and Wonchan Kim and Park, {Young June} and Gijung Ahn",

year = "2002",

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doi = "10.1109/JSSC.2002.804342",

language = "English",

volume = "37",

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journal = "IEEE Journal of Solid-State Circuits",

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AU - Lee, Sang Hyun

AU - Hwang, Moon Sang

AU - Choi, Youngdon

AU - Kim, Sungjoon

AU - Moon, Yongsam

AU - Lee, Bong Joon

AU - Jeong, Deog Kyoon

AU - Kim, Wonchan

AU - Park, Young June

AU - Ahn, Gijung

PY - 2002/12

Y1 - 2002/12

N2 - This paper describes a clock/data recovery circuit (CDR) incorporating a variable-interval 3×-oversampling method for enhanced high-frequency jitter tolerance. The CDR traces the eye-opening region to place the data-sampling clock exactly at the center of data eye, responding to the shape and magnitude of jitter. A sampler with a pair of input-holding switches enables high-speed data sampling with reduced dynamic offset voltage. From the Linearized model of the phase detector, the loop dynamics of the CDR is analyzed. Integrated in a single-chip transceiver with 0.25-μm CMOS technology, the CDR operates at a data rate of 5 Gb/s. The CDR shows a bit error rate of less than 10-13 when the magnitude of data jitter reaches 60.5% of a bit time.

AB - This paper describes a clock/data recovery circuit (CDR) incorporating a variable-interval 3×-oversampling method for enhanced high-frequency jitter tolerance. The CDR traces the eye-opening region to place the data-sampling clock exactly at the center of data eye, responding to the shape and magnitude of jitter. A sampler with a pair of input-holding switches enables high-speed data sampling with reduced dynamic offset voltage. From the Linearized model of the phase detector, the loop dynamics of the CDR is analyzed. Integrated in a single-chip transceiver with 0.25-μm CMOS technology, the CDR operates at a data rate of 5 Gb/s. The CDR shows a bit error rate of less than 10-13 when the magnitude of data jitter reaches 60.5% of a bit time.

KW - Clock/data recovery

KW - Data eye

KW - Deterministic jitter

KW - High-frequency jitter tolerance

KW - Phase detector

KW - Sampler

KW - Serial link

KW - Variable-interval oversampling

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JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

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ER -

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Abstract

Keywords

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