A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Sang Hyun Lee, Moon Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong Joon Lee, Deog Kyoon Jeong, Wonchan Kim, Young June Park, Gijung Ahn

Research output: Contribution to journalArticlepeer-review

53 Scopus citations


This paper describes a clock/data recovery circuit (CDR) incorporating a variable-interval 3×-oversampling method for enhanced high-frequency jitter tolerance. The CDR traces the eye-opening region to place the data-sampling clock exactly at the center of data eye, responding to the shape and magnitude of jitter. A sampler with a pair of input-holding switches enables high-speed data sampling with reduced dynamic offset voltage. From the Linearized model of the phase detector, the loop dynamics of the CDR is analyzed. Integrated in a single-chip transceiver with 0.25-μm CMOS technology, the CDR operates at a data rate of 5 Gb/s. The CDR shows a bit error rate of less than 10-13 when the magnitude of data jitter reaches 60.5% of a bit time.

Original languageEnglish
Pages (from-to)1822-1830
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number12
StatePublished - Dec 2002


  • Clock/data recovery
  • Data eye
  • Deterministic jitter
  • High-frequency jitter tolerance
  • Phase detector
  • Sampler
  • Serial link
  • Variable-interval oversampling


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