A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

This paper describes a clock/data recovery circuit (CDR) incorporating a variable-interval 3×-oversampling method for enhanced high-frequency jitter tolerance. The CDR traces the eye-opening region to place the data-sampling clock exactly at the center of data eye, responding to the shape and magnitude of jitter. A sampler with a pair of input-holding switches enables high-speed data sampling with reduced dynamic offset voltage. From the Linearized model of the phase detector, the loop dynamics of the CDR is analyzed. Integrated in a single-chip transceiver with 0.25-μm CMOS technology, the CDR operates at a data rate of 5 Gb/s. The CDR shows a bit error rate of less than 10^-13 when the magnitude of data jitter reaches 60.5% of a bit time.