A 5 Gb/s 0.25 μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Sang Hyun Lee; Moon Sang Hwang; Youngdon Choi; Sungjoon Kim; Yongsam Moon; Bong Joon Lee; Deog Kyoon Jeong; Wonchan Kim; Young June Park; Gi Jung Ahn

A 5 Gb/s 0.25 μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Sang Hyun Lee
, Moon Sang Hwang
, Youngdon Choi
, Sungjoon Kim
, Yongsam Moon
, Bong Joon Lee
, Deog Kyoon Jeong
, Wonchan Kim
, Young June Park
, Gi Jung Ahn

School of Electrical and Computer Engineering

Seoul National University

Research output: Contribution to journal › Conference article › peer-review

14 Scopus citations

Abstract

A variable-interval oversampling clock/data recovery circuit (CDR) provides robust operation under varying jitter conditions. An eye-measuring loop in the CDR enables data recovery at maximum eye-opening, responding to the amount and shape of jitter. The CDR in 0.25 μm CMOS shows <10^-13 BER for 2⁷-1 PRBS at 5GBaud.

Original language	English
Pages (from-to)	256-257+465+247
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
State	Published - 2002
Event	2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States Duration: 3 Feb 2002 → 7 Feb 2002

Cite this

@article{db459fd4e718458d9b30dd5bfd40c65f,

title = "A 5 Gb/s 0.25 μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit",

abstract = "A variable-interval oversampling clock/data recovery circuit (CDR) provides robust operation under varying jitter conditions. An eye-measuring loop in the CDR enables data recovery at maximum eye-opening, responding to the amount and shape of jitter. The CDR in 0.25 μm CMOS shows <10-13 BER for 27-1 PRBS at 5GBaud.",

author = "Lee, \{Sang Hyun\} and Hwang, \{Moon Sang\} and Youngdon Choi and Sungjoon Kim and Yongsam Moon and Lee, \{Bong Joon\} and Jeong, \{Deog Kyoon\} and Wonchan Kim and Park, \{Young June\} and Ahn, \{Gi Jung\}",

year = "2002",

language = "English",

pages = "256--257+465+247",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2002 IEEE International Solid-State Circuits Conference ; Conference date: 03-02-2002 Through 07-02-2002",

}

TY - JOUR

T1 - A 5 Gb/s 0.25 μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

AU - Lee, Sang Hyun

AU - Hwang, Moon Sang

AU - Choi, Youngdon

AU - Kim, Sungjoon

AU - Moon, Yongsam

AU - Lee, Bong Joon

AU - Jeong, Deog Kyoon

AU - Kim, Wonchan

AU - Park, Young June

AU - Ahn, Gi Jung

PY - 2002

Y1 - 2002

N2 - A variable-interval oversampling clock/data recovery circuit (CDR) provides robust operation under varying jitter conditions. An eye-measuring loop in the CDR enables data recovery at maximum eye-opening, responding to the amount and shape of jitter. The CDR in 0.25 μm CMOS shows <10-13 BER for 27-1 PRBS at 5GBaud.

AB - A variable-interval oversampling clock/data recovery circuit (CDR) provides robust operation under varying jitter conditions. An eye-measuring loop in the CDR enables data recovery at maximum eye-opening, responding to the amount and shape of jitter. The CDR in 0.25 μm CMOS shows <10-13 BER for 27-1 PRBS at 5GBaud.

UR - https://www.scopus.com/pages/publications/20244386651

M3 - Conference article

AN - SCOPUS:20244386651

SN - 0193-6530

SP - 256-257+465+247

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - 2002 IEEE International Solid-State Circuits Conference

Y2 - 3 February 2002 through 7 February 2002

ER -

A 5 Gb/s 0.25 μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

Abstract

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