@inproceedings{986a3dc516144509b9d98d3cb646e71d,
title = "A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS",
abstract = "A 6-b 4x time-interleaved (TI) time-domain interpolating flash ADC is presented for high-speed applications. The dynamic-amplifier-structured voltage-to-time converter (VTC) enables linear zero-crossing interpolation in the time-domain with an interpolation factor of eight, resulting in reduced power consumption and area. A sequential slope-matching offset calibration scheme is proposed not only for VTC offset but also for interpolated zero-crossing accuracy. The prototype 6-bit 10-Gs/s 4x TI flash ADC was implemented in a 65-nm CMOS process and occupied 0.22 mm2 including a 4-to-1 output MUX and 243-times output decimator. The ADC achieves SNDR of 28.9 dB at Nyquist input and a total power consumption of 63 mW under supplies of 0.85 V and 1.1 V for the ADC cores and clock generator + T/Hs, respectively.",
keywords = "ADC, Analog to digital converter, flash ADC, interpolation, offset calibration, time-interleaved ADC",
author = "Oh, {Dong Ryeol} and Kim, {Jong In} and Seo, {Min Jae} and Kim, {Jin Gwang} and Ryu, {Seung Tak}",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 41st European Solid-State Circuits Conference, ESSCIRC 2015 ; Conference date: 14-09-2015 Through 18-09-2015",
year = "2015",
month = oct,
day = "30",
doi = "10.1109/ESSCIRC.2015.7313892",
language = "English",
series = "European Solid-State Circuits Conference",
publisher = "IEEE Computer Society",
pages = "323--326",
editor = "Franz Dielacher and Wolfgang Pribyl and Gernot Hueber",
booktitle = "ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference",
address = "United States",
}