A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL with Nested-Delay Cell and Background Static Phase Offset Calibration

Dong Jin Chang; Min Jae Seo; Hyeok Ki Hong; Seung Tak Ryu

doi:10.1109/TCSII.2017.2689029

A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL with Nested-Delay Cell and Background Static Phase Offset Calibration

Dong Jin Chang
, Min Jae Seo
, Hyeok Ki Hong
, Seung Tak Ryu

School of Advanced Fusion Studies

Korea Advanced Institute of Science and Technology

Research output: Contribution to journal › Article › peer-review

9 Scopus citations

Abstract

This brief presents a wide frequency-range synthesizable multiplying delay-locked-loop with a proposed nested delay cell. Operating in two different modes, the clock generator synthesizes output frequency that ranges from 80 kHz to 680 MHz. Owing to the synthesized finely controlled charge pump and phase detector with background offset calibration, the prototype clock generator achieves a 5.2 ps integrated RMS jitter at 680 MHz output while consuming 0.5 mW under a 1.2 V supply.

Original language	English
Pages (from-to)	281-285
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	65
Issue number	3
DOIs	https://doi.org/10.1109/TCSII.2017.2689029
State	Published - Mar 2018

Keywords

background calibration
Clock generator
multiple delayed locked-loop
static phase offset
synthesizable
wide frequency range

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10.1109/TCSII.2017.2689029

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title = "A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL with Nested-Delay Cell and Background Static Phase Offset Calibration",

abstract = "This brief presents a wide frequency-range synthesizable multiplying delay-locked-loop with a proposed nested delay cell. Operating in two different modes, the clock generator synthesizes output frequency that ranges from 80 kHz to 680 MHz. Owing to the synthesized finely controlled charge pump and phase detector with background offset calibration, the prototype clock generator achieves a 5.2 ps integrated RMS jitter at 680 MHz output while consuming 0.5 mW under a 1.2 V supply.",

keywords = "background calibration, Clock generator, multiple delayed locked-loop, static phase offset, synthesizable, wide frequency range",

author = "Chang, \{Dong Jin\} and Seo, \{Min Jae\} and Hong, \{Hyeok Ki\} and Ryu, \{Seung Tak\}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.",

year = "2018",

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doi = "10.1109/TCSII.2017.2689029",

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AU - Chang, Dong Jin

AU - Seo, Min Jae

AU - Hong, Hyeok Ki

AU - Ryu, Seung Tak

PY - 2018/3

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AB - This brief presents a wide frequency-range synthesizable multiplying delay-locked-loop with a proposed nested delay cell. Operating in two different modes, the clock generator synthesizes output frequency that ranges from 80 kHz to 680 MHz. Owing to the synthesized finely controlled charge pump and phase detector with background offset calibration, the prototype clock generator achieves a 5.2 ps integrated RMS jitter at 680 MHz output while consuming 0.5 mW under a 1.2 V supply.

KW - background calibration

KW - Clock generator

KW - multiple delayed locked-loop

KW - static phase offset

KW - synthesizable

KW - wide frequency range

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JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 3

ER -

A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL with Nested-Delay Cell and Background Static Phase Offset Calibration

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Keywords

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