A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog Kyoon Jeong, Yunho Choi, Hyung Kyu Lim

Research output: Contribution to journalArticlepeer-review

114 Scopus citations


This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to-peak jitter of 150 ps and rms jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6-μm CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.

Original languageEnglish
Pages (from-to)691-699
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number5
StatePublished - May 1997


  • CMOS
  • High speed bus
  • Jitter
  • Oversampling
  • Phase frequency detector
  • Phase locked loop
  • Skew-tolerant
  • Voltage controlled oscillator


Dive into the research topics of 'A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL'. Together they form a unique fingerprint.

Cite this