A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

Sungjoon Kim; Kyeongho Lee; Yongsam Moon; Deog Kyoon Jeong; Yunho Choi; Hyung Kyu Lim

doi:10.1109/9780470545492.ch50

A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog Kyoon Jeong, Yunho Choi, Hyung Kyu Lim

School of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

Abstract

This paper describes an I/O scheme for use in a highspeed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to- peak jitter of 150 ps and nos jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6μm CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.

Original language	English
Title of host publication	Phase-Locking in High-Performance Systems
Subtitle of host publication	From Devices to Architectures
Publisher	Wiley-IEEE Press
Pages	413-421
Number of pages	9
ISBN (Electronic)	9780470545492
ISBN (Print)	0471447277, 9780471447276
DOIs	https://doi.org/10.1109/9780470545492.ch50
State	Published - 1 Jan 2003

Keywords

Charge pumps
Clocks
Jitter
Noise
Phase frequency detector
Phase locked loops
Voltage-controlled oscillators

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10.1109/9780470545492.ch50

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abstract = "This paper describes an I/O scheme for use in a highspeed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to- peak jitter of 150 ps and nos jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6μm CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.",

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AU - Choi, Yunho

AU - Kyu Lim, Hyung

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AB - This paper describes an I/O scheme for use in a highspeed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to- peak jitter of 150 ps and nos jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6μm CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.

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KW - Clocks

KW - Jitter

KW - Noise

KW - Phase frequency detector

KW - Phase locked loops

KW - Voltage-controlled oscillators

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ER -

A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

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Keywords

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