A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

Sungjoon Kim; Kyeongho Lee; Yongsam Moon; Deog Kyoon Jeong; Yunho Choi; Hyung Kyu Lim

doi:10.1109/4.568836

A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog Kyoon Jeong, Yunho Choi, Hyung Kyu Lim

School of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

116 Scopus citations

Abstract

This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to-peak jitter of 150 ps and rms jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6-μm CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.

Original language	English
Pages (from-to)	691-699
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	32
Issue number	5
DOIs	https://doi.org/10.1109/4.568836
State	Published - May 1997

Keywords

CMOS
High speed bus
Jitter
Oversampling
Phase frequency detector
Phase locked loop
Skew-tolerant
Voltage controlled oscillator

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10.1109/4.568836

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abstract = "This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to-peak jitter of 150 ps and rms jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6-μm CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.",

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AU - Choi, Yunho

AU - Lim, Hyung Kyu

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AB - This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to-peak jitter of 150 ps and rms jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6-μm CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.

KW - CMOS

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KW - Jitter

KW - Oversampling

KW - Phase frequency detector

KW - Phase locked loop

KW - Skew-tolerant

KW - Voltage controlled oscillator

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A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

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Keywords

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