A concurrent dual-band CMOS low-noise amplifier for ISM-band application

Hee Sauk Jhon; Hakchul Jung; Min Suk Koo; Hyungcheol Shin

doi:10.1109/SOCDC.2008.4815733

A concurrent dual-band CMOS low-noise amplifier for ISM-band application

Hee Sauk Jhon, Hakchul Jung, Min Suk Koo, Hyungcheol Shin

School of Advanced Fusion Studies

Seoul National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LCladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-μm mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz and 25 GHz, respectively. The proposed LNA exhibits 8.1 mW power consumption from 0.8 V supply and the active chip area including pad is about 720 × 460 μm².

Original language	English
Title of host publication	2008 International SoC Design Conference, ISOCC 2008
Pages	III27-III28
DOIs	https://doi.org/10.1109/SOCDC.2008.4815733
State	Published - 2008
Event	2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of Duration: 24 Nov 2008 → 25 Nov 2008

Publication series

Name	2008 International SoC Design Conference, ISOCC 2008
Volume	3

Conference

Conference	2008 International SoC Design Conference, ISOCC 2008
Country/Territory	Korea, Republic of
City	Busan
Period	24/11/08 → 25/11/08

Keywords

CMOS
Component
Dual-band
LNA

Access to Document

10.1109/SOCDC.2008.4815733

Cite this

@inproceedings{c6e17a270d5b4d2bbaed3fc8dc7c4c23,

title = "A concurrent dual-band CMOS low-noise amplifier for ISM-band application",

abstract = "A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LCladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-μm mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz and 25 GHz, respectively. The proposed LNA exhibits 8.1 mW power consumption from 0.8 V supply and the active chip area including pad is about 720 × 460 μm2.",

keywords = "CMOS, Component, Dual-band, LNA",

author = "Jhon, {Hee Sauk} and Hakchul Jung and Koo, {Min Suk} and Hyungcheol Shin",

year = "2008",

doi = "10.1109/SOCDC.2008.4815733",

language = "English",

isbn = "9781424425990",

series = "2008 International SoC Design Conference, ISOCC 2008",

pages = "III27--III28",

booktitle = "2008 International SoC Design Conference, ISOCC 2008",

note = "2008 International SoC Design Conference, ISOCC 2008 ; Conference date: 24-11-2008 Through 25-11-2008",

}

Jhon, HS, Jung, H, Koo, MS & Shin, H 2008, A concurrent dual-band CMOS low-noise amplifier for ISM-band application. in 2008 International SoC Design Conference, ISOCC 2008., 4815733, 2008 International SoC Design Conference, ISOCC 2008, vol. 3, pp. III27-III28, 2008 International SoC Design Conference, ISOCC 2008, Busan, Korea, Republic of, 24/11/08. https://doi.org/10.1109/SOCDC.2008.4815733

A concurrent dual-band CMOS low-noise amplifier for ISM-band application. / Jhon, Hee Sauk; Jung, Hakchul; Koo, Min Suk et al.
2008 International SoC Design Conference, ISOCC 2008. 2008. p. III27-III28 4815733 (2008 International SoC Design Conference, ISOCC 2008; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A concurrent dual-band CMOS low-noise amplifier for ISM-band application

AU - Jhon, Hee Sauk

AU - Jung, Hakchul

AU - Koo, Min Suk

AU - Shin, Hyungcheol

PY - 2008

Y1 - 2008

N2 - A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LCladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-μm mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz and 25 GHz, respectively. The proposed LNA exhibits 8.1 mW power consumption from 0.8 V supply and the active chip area including pad is about 720 × 460 μm2.

AB - A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LCladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-μm mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz and 25 GHz, respectively. The proposed LNA exhibits 8.1 mW power consumption from 0.8 V supply and the active chip area including pad is about 720 × 460 μm2.

KW - CMOS

KW - Component

KW - Dual-band

KW - LNA

UR - http://www.scopus.com/inward/record.url?scp=67650650026&partnerID=8YFLogxK

U2 - 10.1109/SOCDC.2008.4815733

DO - 10.1109/SOCDC.2008.4815733

M3 - Conference contribution

AN - SCOPUS:67650650026

SN - 9781424425990

T3 - 2008 International SoC Design Conference, ISOCC 2008

SP - III27-III28

BT - 2008 International SoC Design Conference, ISOCC 2008

T2 - 2008 International SoC Design Conference, ISOCC 2008

Y2 - 24 November 2008 through 25 November 2008

ER -

A concurrent dual-band CMOS low-noise amplifier for ISM-band application

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Conference

Keywords

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