@inproceedings{382c98f5126e485a8c7a1f588215b6d9,
title = "A dual PFD phase rotating multi-phase PLL for 5Gbps PCI express Gen2 multi-lane serial link receiver in 0.13um CMOS",
abstract = "A dual phase frequency detector phase-locked loop (PLL) architecture for multi-lane 5Gbps serial link receiver is demonstrated using 0.13urn CMOS. The PLL's 8 multiphase clocks can be rotated altogether digitally with respect to a single fixed phase clock from a main PLL. The phase step resolution is 1/15 of a unit bit interval and the rotation is achieved by adding only one additional phase-frequency detector (PFD) and a charge pump. The rms jitter is 1.2ps for 5Gbps serial link operation. The new PLL occupies 0.015mm2 and consumes 3mA from a 1.2V supply. The small area and low power nature of the architecture is suitable for receivers in multi-lane serial links.",
keywords = "Dual phase frequency detector, Multi-lane, PLL, Serial link",
author = "Sungjoon Kim and Dongyun Lee and Park, {Young Soo} and Yongsam Moon and Daeyun Shim",
year = "2007",
doi = "10.1109/VLSIC.2007.4342732",
language = "English",
isbn = "9784900784048",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
pages = "234--235",
booktitle = "2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers",
note = "2007 Symposium on VLSI Circuits, VLSIC ; Conference date: 14-06-2007 Through 16-06-2007",
}