A dual PFD phase rotating multi-phase PLL for 5Gbps PCI express Gen2 multi-lane serial link receiver in 0.13um CMOS

Sungjoon Kim, Dongyun Lee, Young Soo Park, Yongsam Moon, Daeyun Shim

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

A dual phase frequency detector phase-locked loop (PLL) architecture for multi-lane 5Gbps serial link receiver is demonstrated using 0.13urn CMOS. The PLL's 8 multiphase clocks can be rotated altogether digitally with respect to a single fixed phase clock from a main PLL. The phase step resolution is 1/15 of a unit bit interval and the rotation is achieved by adding only one additional phase-frequency detector (PFD) and a charge pump. The rms jitter is 1.2ps for 5Gbps serial link operation. The new PLL occupies 0.015mm2 and consumes 3mA from a 1.2V supply. The small area and low power nature of the architecture is suitable for receivers in multi-lane serial links.

Original languageEnglish
Title of host publication2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages234-235
Number of pages2
DOIs
StatePublished - 2007
Event2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan
Duration: 14 Jun 200716 Jun 2007

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2007 Symposium on VLSI Circuits, VLSIC
Country/TerritoryJapan
CityKyoto
Period14/06/0716/06/07

Keywords

  • Dual phase frequency detector
  • Multi-lane
  • PLL
  • Serial link

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