A Hardware-efficient Rate Encoding Hardware with Latch-based TRNG

Spiking Neural Networks (SNN) encoding is the data conversion between spikes and continuous real-valued signals, which is an important factor that decisively affects the operation and performance of SNNs. In this study, we analyze and compare the main encoding methods such as conventional rate coding, phase coding, Time to First Spike (TTFS) coding, and burst coding. To measure how efficient they are in practice, commonly used digital circuits were implemented on the Zybo Z7-20, a Field Programmable Gate Array (FPGA) from Xilinx, to measure and compare the hardware complexity and power consumption of each system. Furthermore, for a more efficient encoding scheme, we propose lightweight rate coding, the most basic and biologically plausible form of encoding, by replacing the random number generator, one of the essential components of rate coding, with a cross-coupled inverter to improve energy and area efficiency. To verify the proposed approach, a rate coding circuit and a conventional rate coding circuit are implemented in TSMC 0.18 um in Cadence tool, and the results show that the proposed rate coding reduces area by 29.25% and power by 22.8% compared to the conventional rate coding.