A High-Precision VLSI Winner-Take-All Circuit for Self-Organizing Neural Networks

Design and implementation of a high-precision VLSI winner-take-all (WTA) circuit that can be arranged to process 1024 inputs are presented. The cascade configuration can be used to significantly increase the competition resolution and maintain a high-speed operation for a large-scale network. The total bias current increases in proportion to the number of circuit cells so that a nearly constant response time is achieved. In addition, a unique dynamic current steering method is used to ensure only a single winner exits in the final output. Experimental results of the prototype chip fabricated by a 2-μm CMOS technology show that a cell can be a winner if its input is larger than those of the other cells by 15 mV. The measured response time is around 50 ns at a 1-pF load capacitance. This analog winner-take-all circuit is a key module in the competitive layer of self-organization neural networks.