A high-speed ATM switch with multiple common memories

Research output: Contribution to conferencePaperpeer-review


We consider a common-memory type N × N ATM switch, where CM block consists of K (K ≥ N) sub-memories. We propose an address assigning algorithm to avoid input/output contentions so that we can have the read/write speed of each SM as low as the interface port speed. Taking replication-at-sending approach, we pursue memory and bandwidth efficiency for multicast cell output. We evaluate the system in terms of cell loss ratio and average delay time. We take into account two loss factors: 1) the failure of scheduling to avoid the input/output contentions and 2) overflow in the CM block.

Original languageEnglish
Number of pages5
StatePublished - 2001
EventIEEE Global Telecommunicatins Conference GLOBECOM'01 - San Antonio, TX, United States
Duration: 25 Nov 200129 Nov 2001


ConferenceIEEE Global Telecommunicatins Conference GLOBECOM'01
Country/TerritoryUnited States
CitySan Antonio, TX


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