A high-speed ATM switch with multiple common memories

Sang H. Kang

A high-speed ATM switch with multiple common memories

School of Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

We consider a common-memory type N × N ATM switch, where CM block consists of K (K ≥ N) sub-memories. We propose an address assigning algorithm to avoid input/output contentions so that we can have the read/write speed of each SM as low as the interface port speed. Taking replication-at-sending approach, we pursue memory and bandwidth efficiency for multicast cell output. We evaluate the system in terms of cell loss ratio and average delay time. We take into account two loss factors: 1) the failure of scheduling to avoid the input/output contentions and 2) overflow in the CM block.

Original language	English
Pages	2645-2649
Number of pages	5
State	Published - 2001
Event	IEEE Global Telecommunicatins Conference GLOBECOM'01 - San Antonio, TX, United States Duration: 25 Nov 2001 → 29 Nov 2001

Conference

Conference	IEEE Global Telecommunicatins Conference GLOBECOM'01
Country/Territory	United States
City	San Antonio, TX
Period	25/11/01 → 29/11/01

Cite this

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abstract = "We consider a common-memory type N × N ATM switch, where CM block consists of K (K ≥ N) sub-memories. We propose an address assigning algorithm to avoid input/output contentions so that we can have the read/write speed of each SM as low as the interface port speed. Taking replication-at-sending approach, we pursue memory and bandwidth efficiency for multicast cell output. We evaluate the system in terms of cell loss ratio and average delay time. We take into account two loss factors: 1) the failure of scheduling to avoid the input/output contentions and 2) overflow in the CM block.",

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AB - We consider a common-memory type N × N ATM switch, where CM block consists of K (K ≥ N) sub-memories. We propose an address assigning algorithm to avoid input/output contentions so that we can have the read/write speed of each SM as low as the interface port speed. Taking replication-at-sending approach, we pursue memory and bandwidth efficiency for multicast cell output. We evaluate the system in terms of cell loss ratio and average delay time. We take into account two loss factors: 1) the failure of scheduling to avoid the input/output contentions and 2) overflow in the CM block.

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M3 - Paper

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T2 - IEEE Global Telecommunicatins Conference GLOBECOM'01

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ER -

A high-speed ATM switch with multiple common memories

Abstract

Conference

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