A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC

Young Ju Kim, Hee Cheol Choi, Pil Seon Yoo, Dong Suk Lee, Joong Ho Choi, Seung Hoon Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

A 12b 2MS/s cyclic ADC achieves low power consumption with a single-ended rail-to-rail input signal range of 3.3Vp-p. The proposed voltage reference scheme directly employing power supply voltages implements an offset voltage less than 1mV without well-known calibration and trimming techniques. The prototype ADC in a 0.18μm CMOS technology demonstrates the effective number of bits of 11.48 for a 100kHz full-scale input at 2MS/s. The ADC with an active die area of 0.12mm2 consumes 3.6mW at 2MS/s and 3.3V(analog)/1.8V (digital).

Original languageEnglish
Title of host publicationProceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Pages17-20
Number of pages4
DOIs
StatePublished - 2008
EventAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China
Duration: 30 Nov 20083 Dec 2008

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

ConferenceAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Country/TerritoryChina
CityMacao
Period30/11/083/12/08

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