A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC

Young Ju Kim; Hee Cheol Choi; Pil Seon Yoo; Dong Suk Lee; Joong Ho Choi; Seung Hoon Lee

doi:10.1109/APCCAS.2008.4745949

A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC

Young Ju Kim, Hee Cheol Choi, Pil Seon Yoo, Dong Suk Lee, Joong Ho Choi, Seung Hoon Lee

School of Electrical and Computer Engineering

Sogang University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

A 12b 2MS/s cyclic ADC achieves low power consumption with a single-ended rail-to-rail input signal range of 3.3Vp-p. The proposed voltage reference scheme directly employing power supply voltages implements an offset voltage less than 1mV without well-known calibration and trimming techniques. The prototype ADC in a 0.18μm CMOS technology demonstrates the effective number of bits of 11.48 for a 100kHz full-scale input at 2MS/s. The ADC with an active die area of 0.12mm² consumes 3.6mW at 2MS/s and 3.3V(analog)/1.8V (digital).

Original language	English
Title of host publication	Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Pages	17-20
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2008.4745949
State	Published - 2008
Event	APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China Duration: 30 Nov 2008 → 3 Dec 2008

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Country/Territory	China
City	Macao
Period	30/11/08 → 3/12/08

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10.1109/APCCAS.2008.4745949

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Kim, Y. J., Choi, H. C., Yoo, P. S., Lee, D. S., Choi, J. H., & Lee, S. H. (2008). A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC. In Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (pp. 17-20). Article 4745949 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2008.4745949

@inproceedings{b040daf04f544228aab5e9cd1ba9f9fe,

title = "A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC",

abstract = "A 12b 2MS/s cyclic ADC achieves low power consumption with a single-ended rail-to-rail input signal range of 3.3Vp-p. The proposed voltage reference scheme directly employing power supply voltages implements an offset voltage less than 1mV without well-known calibration and trimming techniques. The prototype ADC in a 0.18μm CMOS technology demonstrates the effective number of bits of 11.48 for a 100kHz full-scale input at 2MS/s. The ADC with an active die area of 0.12mm2 consumes 3.6mW at 2MS/s and 3.3V(analog)/1.8V (digital).",

author = "Kim, \{Young Ju\} and Choi, \{Hee Cheol\} and Yoo, \{Pil Seon\} and Lee, \{Dong Suk\} and Choi, \{Joong Ho\} and Lee, \{Seung Hoon\}",

year = "2008",

doi = "10.1109/APCCAS.2008.4745949",

language = "English",

isbn = "9781424423422",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "17--20",

booktitle = "Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems",

note = "APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems ; Conference date: 30-11-2008 Through 03-12-2008",

}

Kim, YJ, Choi, HC, Yoo, PS, Lee, DS, Choi, JH & Lee, SH 2008, A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC. in Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems., 4745949, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 17-20, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, 30/11/08. https://doi.org/10.1109/APCCAS.2008.4745949

A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC. / Kim, Young Ju; Choi, Hee Cheol; Yoo, Pil Seon et al.
Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. 2008. p. 17-20 4745949 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Choi, Joong Ho

AU - Lee, Seung Hoon

PY - 2008

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N2 - A 12b 2MS/s cyclic ADC achieves low power consumption with a single-ended rail-to-rail input signal range of 3.3Vp-p. The proposed voltage reference scheme directly employing power supply voltages implements an offset voltage less than 1mV without well-known calibration and trimming techniques. The prototype ADC in a 0.18μm CMOS technology demonstrates the effective number of bits of 11.48 for a 100kHz full-scale input at 2MS/s. The ADC with an active die area of 0.12mm2 consumes 3.6mW at 2MS/s and 3.3V(analog)/1.8V (digital).

AB - A 12b 2MS/s cyclic ADC achieves low power consumption with a single-ended rail-to-rail input signal range of 3.3Vp-p. The proposed voltage reference scheme directly employing power supply voltages implements an offset voltage less than 1mV without well-known calibration and trimming techniques. The prototype ADC in a 0.18μm CMOS technology demonstrates the effective number of bits of 11.48 for a 100kHz full-scale input at 2MS/s. The ADC with an active die area of 0.12mm2 consumes 3.6mW at 2MS/s and 3.3V(analog)/1.8V (digital).

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DO - 10.1109/APCCAS.2008.4745949

M3 - Conference contribution

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SN - 9781424423422

T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

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BT - Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

T2 - APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

Y2 - 30 November 2008 through 3 December 2008

ER -

A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC

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