A low-power 100 MHz analog FIR filter for PRML equalization

Joongho Choi, Jungryoul Choi

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


This paper presents design of a low-power 100 MHz analog FIR filter for PRML equalization used in the read channel of hard disk drives. The chip consists of 16 channels to provide 15-tap FIR filter operation. By using rotating clocks for sample/hold operation with one dummy channel, timing constraints can be relieved, which results in low-power consumption. The chip incorporates the parallel array of sample-and-hold amplifiers for analog delay line. The sample-and-hold amplifier includes the open-loop unity-gain amplifier with gain-control circuit using replica-biasing scheme, which also improves uniformity among amplifiers. It was fabricated in a 0.8-μm CMOS technology and consumes power of 200 mW for ±1.65 V power supply voltage.

Original languageEnglish
Pages (from-to)225-238
Number of pages14
JournalAnalog Integrated Circuits and Signal Processing
Issue number3
StatePublished - Sep 2001


  • Analog FIR filter
  • Gain-control circuit
  • PRML equalizer
  • Sample-and-hold amplifier


Dive into the research topics of 'A low-power 100 MHz analog FIR filter for PRML equalization'. Together they form a unique fingerprint.

Cite this