A low-power sigma-delta modulator for wireless communication receivers using adaptive biasing circuitry and cascaded comparator scheme

This paper represents the low-power signal-delta (∑Δ) modulator for wireless communication receiver applications. The 2nd-order modulator has a single-loop structure with 11 quantization levels. An adaptive biasing scheme of the operational amplifier and cascaded comparator scheme are proposed in order to save the power consumption. The DAC with three-level references including the analog ground voltage can make the modulator be implemented with half of the input capacitances without degradation of linearity characteristics with the help of dynamic element matching technique. Peak SNR values of 74 dB and 68dB are achieved with the input bandwidths of 615 kHz and 1.92 MHz for CDMA-2000 and WCDMA applications, respectively. The modulator is fabricated in a 0.13-μm standard digital CMOS technology and dissipates 4.3 mA for a single supply voltage of 2.8 V.