@inproceedings{8fc21eef55d0479e96b219790c50134f,
title = "A multiphase delay-locked loop for 0.125-2Gbps 0.18μm CMOS transmitter",
abstract = "A 0.18-μm CMOS DLL generates equally-spaced multiphase clocks over 16x range from 31.25 to 500MHz using a duty-cycle corrector and a lock detector with 32x lock range, which is at least 3.5x wider comparing with conventional multiphase DLL's. Measured TX data eyes have <4% eye unevenness, which is equivalent to <1% clock unevenness, over the data rates of 0.125 to 2Gbps.",
keywords = "DLL, Duty cycle, Lock detector, Multiphase",
author = "Yongsam Moon and Daeyun Shim",
year = "2006",
language = "English",
isbn = "1424400066",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
pages = "35--36",
booktitle = "2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers",
note = "2006 Symposium on VLSI Circuits, VLSIC ; Conference date: 15-06-2006 Through 17-06-2006",
}