Abstract
A simple Two-Step Search (2SS) algorithm for motion estimation and its FPGA implementation are proposed in this paper. The algorithm has an excellent trade-off between performance and hardware cost. Simulation results show that the performance of the proposed algorithm is very close to that of the classical Full Search (FS) algorithm. The proposed algorithm has a very low computational complexity. By using only two processing elements, the proposed architecture has low hardware cost, low memory and bandwidth requirements, and high speed. With its low resource requirements, the algorithm may be used in mobile real-time video applications. We have prototyped it in an FPGA to be used as an IP for SoPC (system-on-a-programmable-chip) solutions.
| Original language | English |
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| Pages | A383-A386 |
| State | Published - 2004 |
| Event | IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering - Chiang Mai, Thailand Duration: 21 Nov 2004 → 24 Nov 2004 |
Conference
| Conference | IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering |
|---|---|
| Country/Territory | Thailand |
| City | Chiang Mai |
| Period | 21/11/04 → 24/11/04 |