A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link

Yongsam Moon; Young Soo Park; Namhoon Kim; Gijung Ahn; Hyun J. Shin; Deog Kyoon Jeong

doi:10.1109/JSSC.2004.826311

A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link

Yongsam Moon, Young Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog Kyoon Jeong

School of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

A quad-channel 0.6-3.2 Gb/s/channnel transceiver using eight independent phase-locked loops (PLLs) shows a 1-ps rms random jitter performance without interchannel interference. The PLL employs a folded starved inverter with high supply/substrate noise immunity and an analog coarse-tuning scheme for both seamless frequency acquisition and N-fold voltage-controlled- oscillator (VCO) gain reduction. A fixed-interval charge pumping is adopted for wide pumping-current range and large jitter tolerance. A wide-range delayed-locked loop (DLL) is utilized as a clock and reset generator for an elastic buffer. The transceiver, implemented in a 0.18-μm CMOS technology, operates across a 30-in FR-4 backplane up to 3.2 Gb/s/ch with a bit-error rate of less than 10^-13.

Original language	English
Pages (from-to)	795-803
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	39
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.2004.826311
State	Published - May 2004

Keywords

Backplane transceiver
Clock and data recovery (CDR)
Coarse tuning
Delay-locked loop (DLL)
Folded starved inverter
Phase-locked loop (PLL)
Pre-emphasis
Serial link

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10.1109/JSSC.2004.826311

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title = "A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link",

abstract = "A quad-channel 0.6-3.2 Gb/s/channnel transceiver using eight independent phase-locked loops (PLLs) shows a 1-ps rms random jitter performance without interchannel interference. The PLL employs a folded starved inverter with high supply/substrate noise immunity and an analog coarse-tuning scheme for both seamless frequency acquisition and N-fold voltage-controlled- oscillator (VCO) gain reduction. A fixed-interval charge pumping is adopted for wide pumping-current range and large jitter tolerance. A wide-range delayed-locked loop (DLL) is utilized as a clock and reset generator for an elastic buffer. The transceiver, implemented in a 0.18-μm CMOS technology, operates across a 30-in FR-4 backplane up to 3.2 Gb/s/ch with a bit-error rate of less than 10-13.",

keywords = "Backplane transceiver, Clock and data recovery (CDR), Coarse tuning, Delay-locked loop (DLL), Folded starved inverter, Phase-locked loop (PLL), Pre-emphasis, Serial link",

author = "Yongsam Moon and Park, {Young Soo} and Namhoon Kim and Gijung Ahn and Shin, {Hyun J.} and Jeong, {Deog Kyoon}",

year = "2004",

month = may,

doi = "10.1109/JSSC.2004.826311",

language = "English",

volume = "39",

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AU - Moon, Yongsam

AU - Park, Young Soo

AU - Kim, Namhoon

AU - Ahn, Gijung

AU - Shin, Hyun J.

AU - Jeong, Deog Kyoon

PY - 2004/5

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N2 - A quad-channel 0.6-3.2 Gb/s/channnel transceiver using eight independent phase-locked loops (PLLs) shows a 1-ps rms random jitter performance without interchannel interference. The PLL employs a folded starved inverter with high supply/substrate noise immunity and an analog coarse-tuning scheme for both seamless frequency acquisition and N-fold voltage-controlled- oscillator (VCO) gain reduction. A fixed-interval charge pumping is adopted for wide pumping-current range and large jitter tolerance. A wide-range delayed-locked loop (DLL) is utilized as a clock and reset generator for an elastic buffer. The transceiver, implemented in a 0.18-μm CMOS technology, operates across a 30-in FR-4 backplane up to 3.2 Gb/s/ch with a bit-error rate of less than 10-13.

AB - A quad-channel 0.6-3.2 Gb/s/channnel transceiver using eight independent phase-locked loops (PLLs) shows a 1-ps rms random jitter performance without interchannel interference. The PLL employs a folded starved inverter with high supply/substrate noise immunity and an analog coarse-tuning scheme for both seamless frequency acquisition and N-fold voltage-controlled- oscillator (VCO) gain reduction. A fixed-interval charge pumping is adopted for wide pumping-current range and large jitter tolerance. A wide-range delayed-locked loop (DLL) is utilized as a clock and reset generator for an elastic buffer. The transceiver, implemented in a 0.18-μm CMOS technology, operates across a 30-in FR-4 backplane up to 3.2 Gb/s/ch with a bit-error rate of less than 10-13.

KW - Backplane transceiver

KW - Clock and data recovery (CDR)

KW - Coarse tuning

KW - Delay-locked loop (DLL)

KW - Folded starved inverter

KW - Phase-locked loop (PLL)

KW - Pre-emphasis

KW - Serial link

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JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 5

ER -

A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link

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Keywords

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