A rail-to-rail input 12b 2 MS/s 0.18 μm CMOS cyclic ADC for touch screen applications

A 12b 2 MS/s cyclic ADC processing 3.3 Vpp single-ended rail-to-rail input signals is presented. The proposed ADC demonstrates an offset voltage less than 1 mV without well-known calibration and trimming techniques although power supplies are directly employed as voltage references. The SHA-free input sampling scheme and the two-stage switched op-amp discussed in this work reduce power dissipation, while the comparators based on capacitor-divided voltage references show a matched full-scale performance between two flash sub ADCs. The prototype ADC in a 0.18 μm 1P6M CMOS demonstrates the effective number of bits of 11.48 for a 100 kHz fullscale input at 2 MS/s. The ADC with an active die area of 0.12 mm² consumes 3.6 mW at 2 MS/s and 3.3 V (analog)/1.8 V (digital).