A reusable code-based SAR ADC design with CDAC compiler and synthesizable analog building blocks

Min Jae Seo; Yi Ju Roh; Dong Jin Chang; Wan Kim; Ye Dam Kim; Seung Tak Ryu

doi:10.1109/TCSII.2018.2822811

A reusable code-based SAR ADC design with CDAC compiler and synthesizable analog building blocks

Min Jae Seo
, Yi Ju Roh
, Dong Jin Chang
, Wan Kim
, Ye Dam Kim
, Seung Tak Ryu

School of Advanced Fusion Studies

Korea Advanced Institute of Science and Technology

Research output: Contribution to journal › Article › peer-review

43 Scopus citations

Abstract

This brief proposes a code-reusable design methodology for synthesizable successive approximation register (SAR) ADCs based on the digital design flow to significantly reduce design effort. The SAR ADCs are composed of a capacitor-DAC (CDAC) macro cell generated by a CDAC compiler and analog functional blocks implemented utilizing digital standard cells. Two prototypes of SAR ADCs (12-bit 100 kS/s and 11-bit 50 MS/s) are fabricated in different CMOS processes (180 nm and 28 nm). The prototype ADCs prove the effectiveness of the proposed design methodology with comparable performances with full-custom designed SAR ADCs.

Original language	English
Article number	8331129
Pages (from-to)	1904-1908
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	65
Issue number	12
DOIs	https://doi.org/10.1109/TCSII.2018.2822811
State	Published - Dec 2018

Keywords

Analog circuit synthesis
Capacitor-DAC (CDAC) compiler
Design methodology
Skewed NAND-based comparator
Standard cell
Successive approximation register (SAR) ADC
Synthesizable bootstrapped switch

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10.1109/TCSII.2018.2822811

Cite this

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title = "A reusable code-based SAR ADC design with CDAC compiler and synthesizable analog building blocks",

abstract = "This brief proposes a code-reusable design methodology for synthesizable successive approximation register (SAR) ADCs based on the digital design flow to significantly reduce design effort. The SAR ADCs are composed of a capacitor-DAC (CDAC) macro cell generated by a CDAC compiler and analog functional blocks implemented utilizing digital standard cells. Two prototypes of SAR ADCs (12-bit 100 kS/s and 11-bit 50 MS/s) are fabricated in different CMOS processes (180 nm and 28 nm). The prototype ADCs prove the effectiveness of the proposed design methodology with comparable performances with full-custom designed SAR ADCs.",

keywords = "Analog circuit synthesis, Capacitor-DAC (CDAC) compiler, Design methodology, Skewed NAND-based comparator, Standard cell, Successive approximation register (SAR) ADC, Synthesizable bootstrapped switch",

author = "Seo, \{Min Jae\} and Roh, \{Yi Ju\} and Chang, \{Dong Jin\} and Wan Kim and Kim, \{Ye Dam\} and Ryu, \{Seung Tak\}",

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AU - Ryu, Seung Tak

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A reusable code-based SAR ADC design with CDAC compiler and synthesizable analog building blocks

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Keywords

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