A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability

Min Jae Seo; Dong Hwan Jin; Ye Dam Kim; Jong Pal Kim; Dong Jin Chang; Won Mook Lim; Jae Hyun Chung; Chang Un Park; Eun Ji An; Seung Tak Ryu

doi:10.1109/A-SSCC47793.2019.9056894

A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability

Min Jae Seo, Dong Hwan Jin, Ye Dam Kim, Jong Pal Kim, Dong Jin Chang, Won Mook Lim, Jae Hyun Chung, Chang Un Park, Eun Ji An, Seung Tak Ryu

School of Advanced Fusion Studies

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

This paper presents a power-efficient buffer-embedding successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a core power supply for the source-follower buffer, having a rail-to-rail signal swing owing to the capacitive level shifting bias scheme. In conjunction with 8x oversampling and the power-saving skip-reset technique that has the inherent chopping capability, the prototype 180nm CMOS 12b ADC operating at a 5.12 MS/s sampling rate achieved a 74.8 dB SNDR under a 1.5V supply voltage.

Original language	English
Title of host publication	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	189-192
Number of pages	4
ISBN (Electronic)	9781728151069
DOIs	https://doi.org/10.1109/A-SSCC47793.2019.9056894
State	Published - Nov 2019
Event	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China Duration: 4 Nov 2019 → 6 Nov 2019

Publication series

Name	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Conference

Conference	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Country/Territory	China
City	Macao
Period	4/11/19 → 6/11/19

Keywords

analog-to-digtal converter (ADC)
capacitive level-shifting
loop-embedded input buffer
low power
push-pull source follower
successive approximation register (SAR)

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10.1109/A-SSCC47793.2019.9056894

Cite this

Seo, M. J., Jin, D. H., Kim, Y. D., Kim, J. P., Chang, D. J., Lim, W. M., Chung, J. H., Park, C. U., An, E. J., & Ryu, S. T. (2019). A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 (pp. 189-192). Article 9056894 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/A-SSCC47793.2019.9056894

Seo, Min Jae ; Jin, Dong Hwan ; Kim, Ye Dam et al. / A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 189-192 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019).

@inproceedings{9e69c1e8f1eb4c6c963c191bb23877e9,

title = "A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability",

abstract = "This paper presents a power-efficient buffer-embedding successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a core power supply for the source-follower buffer, having a rail-to-rail signal swing owing to the capacitive level shifting bias scheme. In conjunction with 8x oversampling and the power-saving skip-reset technique that has the inherent chopping capability, the prototype 180nm CMOS 12b ADC operating at a 5.12 MS/s sampling rate achieved a 74.8 dB SNDR under a 1.5V supply voltage.",

keywords = "analog-to-digtal converter (ADC), capacitive level-shifting, loop-embedded input buffer, low power, push-pull source follower, successive approximation register (SAR)",

author = "Seo, {Min Jae} and Jin, {Dong Hwan} and Kim, {Ye Dam} and Kim, {Jong Pal} and Chang, {Dong Jin} and Lim, {Won Mook} and Chung, {Jae Hyun} and Park, {Chang Un} and An, {Eun Ji} and Ryu, {Seung Tak}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 ; Conference date: 04-11-2019 Through 06-11-2019",

year = "2019",

month = nov,

doi = "10.1109/A-SSCC47793.2019.9056894",

language = "English",

series = "Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "189--192",

booktitle = "Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019",

address = "United States",

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Seo, MJ, Jin, DH, Kim, YD, Kim, JP, Chang, DJ, Lim, WM, Chung, JH, Park, CU, An, EJ & Ryu, ST 2019, A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. in Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019., 9056894, Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Institute of Electrical and Electronics Engineers Inc., pp. 189-192, 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macao, China, 4/11/19. https://doi.org/10.1109/A-SSCC47793.2019.9056894

A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. / Seo, Min Jae; Jin, Dong Hwan; Kim, Ye Dam et al.
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 189-192 9056894 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Seo, Min Jae

AU - Jin, Dong Hwan

AU - Kim, Ye Dam

AU - Kim, Jong Pal

AU - Chang, Dong Jin

AU - Lim, Won Mook

AU - Chung, Jae Hyun

AU - Park, Chang Un

AU - An, Eun Ji

AU - Ryu, Seung Tak

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N2 - This paper presents a power-efficient buffer-embedding successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a core power supply for the source-follower buffer, having a rail-to-rail signal swing owing to the capacitive level shifting bias scheme. In conjunction with 8x oversampling and the power-saving skip-reset technique that has the inherent chopping capability, the prototype 180nm CMOS 12b ADC operating at a 5.12 MS/s sampling rate achieved a 74.8 dB SNDR under a 1.5V supply voltage.

AB - This paper presents a power-efficient buffer-embedding successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a core power supply for the source-follower buffer, having a rail-to-rail signal swing owing to the capacitive level shifting bias scheme. In conjunction with 8x oversampling and the power-saving skip-reset technique that has the inherent chopping capability, the prototype 180nm CMOS 12b ADC operating at a 5.12 MS/s sampling rate achieved a 74.8 dB SNDR under a 1.5V supply voltage.

KW - analog-to-digtal converter (ADC)

KW - capacitive level-shifting

KW - loop-embedded input buffer

KW - low power

KW - push-pull source follower

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BT - Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

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Seo MJ, Jin DH, Kim YD, Kim JP, Chang DJ, Lim WM et al. A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 189-192. 9056894. (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019). doi: 10.1109/A-SSCC47793.2019.9056894

A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability

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Keywords

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