A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability

  • Min Jae Seo
  • , Dong Hwan Jin
  • , Ye Dam Kim
  • , Jong Pal Kim
  • , Dong Jin Chang
  • , Won Mook Lim
  • , Jae Hyun Chung
  • , Chang Un Park
  • , Eun Ji An
  • , Seung Tak Ryu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

This paper presents a power-efficient buffer-embedding successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a core power supply for the source-follower buffer, having a rail-to-rail signal swing owing to the capacitive level shifting bias scheme. In conjunction with 8x oversampling and the power-saving skip-reset technique that has the inherent chopping capability, the prototype 180nm CMOS 12b ADC operating at a 5.12 MS/s sampling rate achieved a 74.8 dB SNDR under a 1.5V supply voltage.

Original languageEnglish
Title of host publicationProceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages189-192
Number of pages4
ISBN (Electronic)9781728151069
DOIs
StatePublished - Nov 2019
Event15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China
Duration: 4 Nov 20196 Nov 2019

Publication series

NameProceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Conference

Conference15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Country/TerritoryChina
CityMacao
Period4/11/196/11/19

Keywords

  • analog-to-digtal converter (ADC)
  • capacitive level-shifting
  • loop-embedded input buffer
  • low power
  • push-pull source follower
  • successive approximation register (SAR)

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