@inproceedings{e1b6b492f43e477b9f4c6194f9571be3,
title = "A study on gate-AU-around (GAA) polycrystalline silicon channel SONOS flash memory",
abstract = "In this study, the gate-all-around (GAA) poly-Si channel flash memories with charge trap layer (Si3N4) have been successfully fabricated. Electric characteristics of fabricated devices including threshold voltage shift with program/erase operation have been investigated. Gate configurations were structured differently according to each defined channel width. Results show that devices with gate-all-around structure have superior program efficiency. To investigate the effect of gate configuration on the program efficiency, TCAD simulation was carried out.",
keywords = "SONOS flash memory, charge trap memory, gate-all-around (GAA)",
author = "Seo, {Joo Yun} and Lee, {Sang Ho} and Yoon Kim and Park, {Se Hwan} and Wandong Kim and Kim, {Do Bin} and Park, {Byung Gook}",
year = "2013",
doi = "10.1109/INEC.2013.6465956",
language = "English",
isbn = "9781467348416",
series = "Proceedings - Winter Simulation Conference",
pages = "69--71",
booktitle = "Proceedings of the 2013 IEEE 5th International Nanoelectronics Conference, INEC 2013",
note = "2013 IEEE 5th International Nanoelectronics Conference, INEC 2013 ; Conference date: 02-01-2013 Through 04-01-2013",
}