A VLSI Architecture for a Pel Recursive Motion Estimation Algorithm

The pel recursive motion estimation is one of two methods currently being used for predictive coding of time-varying image. Motivated by a growing demand for efficient motion compensated (MC) coder operating in real time, we propose a VLSI architecture based on parallel and pipelined processing for implementing the pel recursive motion estimation algorithm. In order to maximize the processing concurrency, the displacement estimation process is divided into its integer and fractional part calculations, and the displacement estimation and the interpolation calculations are decoupled so that each calculation can be computed on separate processors. The proposed architecture, which exploits pipelining, parallelism and simple adjacent neighbor interprocessor wiring, is appropriate for the VLSI implementation. Performance evaluation of the proposed architecture on the real image sequences are presented. In addition, issues involved in the fixed-point arithmetic and coding are also discussed.