TY - GEN
T1 - A VLSI implementation of minutiae extraction for secure fingerprint authentication
AU - Pan, Sung Bum
AU - Moon, Daesung
AU - Kim, Kichul
AU - Chung, Yongwha
PY - 2006
Y1 - 2006
N2 - To heighten the biometrics security level, the biometrics feature extraction and verification need to be performed within smart cards, not in external card readers. However, the smart card chip has very limited processing capability, and typical fingerprint feature extraction and verification algorithms may not be executed on a state-of-the-art smart card. Therefore, this paper presents an System-on-Chip(SoC) implementation of the fingerprint feature extraction algorithm which can be integrated into smart cards. To implement the ridge-following algorithm onto the resource-constrained SoCs, the algorithm has been modified to increase the efficiency of the hardware. Each functional block of the algorithm has been implemented in hardware or in software by considering its computational complexity, cost and utilization of the hardware, and efficiency of the entire system. The proposed system operated in 50MHz, and 20-50 minutiae could be extracted from typical 248×292 fingerprint images in real time with our small area implementation(97K gates). Our current implementation developed as an IP for SoCs targeted for ARM CPU andAMBA bus can also be extended for many other smart card configurations.
AB - To heighten the biometrics security level, the biometrics feature extraction and verification need to be performed within smart cards, not in external card readers. However, the smart card chip has very limited processing capability, and typical fingerprint feature extraction and verification algorithms may not be executed on a state-of-the-art smart card. Therefore, this paper presents an System-on-Chip(SoC) implementation of the fingerprint feature extraction algorithm which can be integrated into smart cards. To implement the ridge-following algorithm onto the resource-constrained SoCs, the algorithm has been modified to increase the efficiency of the hardware. Each functional block of the algorithm has been implemented in hardware or in software by considering its computational complexity, cost and utilization of the hardware, and efficiency of the entire system. The proposed system operated in 50MHz, and 20-50 minutiae could be extracted from typical 248×292 fingerprint images in real time with our small area implementation(97K gates). Our current implementation developed as an IP for SoCs targeted for ARM CPU andAMBA bus can also be extended for many other smart card configurations.
UR - http://www.scopus.com/inward/record.url?scp=38949099059&partnerID=8YFLogxK
U2 - 10.1109/ICCIAS.2006.295249
DO - 10.1109/ICCIAS.2006.295249
M3 - Conference contribution
AN - SCOPUS:38949099059
SN - 1424406056
SN - 9781424406050
T3 - 2006 International Conference on Computational Intelligence and Security, ICCIAS 2006
SP - 1217
EP - 1220
BT - 2006 International Conference on Computational Intelligence and Security, ICCIAS 2006
PB - IEEE Computer Society
T2 - 2006 International Conference on Computational Intelligence and Security, ICCIAS 2006
Y2 - 3 October 2006 through 6 October 2006
ER -