A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond

Ki Tae Park; Myounggon Kang; Doogon Kim; Soonwook Hwang; Yeong Taek Lee; Changhyun Kim; Kinam Kim

doi:10.1109/VLSIC.2007.4342709

A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond

Ki Tae Park
, Myounggon Kang
, Doogon Kim
, Soonwook Hwang
, Yeong Taek Lee
, Changhyun Kim
, Kinam Kim

School of Advanced Fusion Studies

Samsung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

24 Scopus citations

Abstract

A new page architecture with temporary LSB storing program scheme is presented as a breakthrough solution for sub-40nm FG (Floating-gate) MLC NAND flash memories and beyond. Without program speed degradation, the proposed method is able to eliminate 100% BL cell-to-cell and almost 50% WL cell-to-cell coupling interferences which are well known as a most critical scaling barrier for FG NAND flash memories.

Original language	English
Title of host publication	2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages	188-189
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2007.4342709
State	Published - 2007
Event	2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan Duration: 14 Jun 2007 → 16 Jun 2007

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2007 Symposium on VLSI Circuits, VLSIC
Country/Territory	Japan
City	Kyoto
Period	14/06/07 → 16/06/07

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10.1109/VLSIC.2007.4342709

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Park, K. T., Kang, M., Kim, D., Hwang, S., Lee, Y. T., Kim, C., & Kim, K. (2007). A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond. In 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 188-189). Article 4342709 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2007.4342709

@inproceedings{c102900bd69341d1b15c13fe87dafc90,

title = "A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond",

abstract = "A new page architecture with temporary LSB storing program scheme is presented as a breakthrough solution for sub-40nm FG (Floating-gate) MLC NAND flash memories and beyond. Without program speed degradation, the proposed method is able to eliminate 100\% BL cell-to-cell and almost 50\% WL cell-to-cell coupling interferences which are well known as a most critical scaling barrier for FG NAND flash memories.",

author = "Park, \{Ki Tae\} and Myounggon Kang and Doogon Kim and Soonwook Hwang and Lee, \{Yeong Taek\} and Changhyun Kim and Kinam Kim",

year = "2007",

doi = "10.1109/VLSIC.2007.4342709",

language = "English",

isbn = "9784900784048",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "188--189",

booktitle = "2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers",

note = "2007 Symposium on VLSI Circuits, VLSIC ; Conference date: 14-06-2007 Through 16-06-2007",

}

Park, KT, Kang, M, Kim, D, Hwang, S, Lee, YT, Kim, C & Kim, K 2007, A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond. in 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers., 4342709, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 188-189, 2007 Symposium on VLSI Circuits, VLSIC, Kyoto, Japan, 14/06/07. https://doi.org/10.1109/VLSIC.2007.4342709

A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond. / Park, Ki Tae; Kang, Myounggon; Kim, Doogon et al.
2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. 2007. p. 188-189 4342709 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Park, Ki Tae

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AU - Hwang, Soonwook

AU - Lee, Yeong Taek

AU - Kim, Changhyun

AU - Kim, Kinam

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AB - A new page architecture with temporary LSB storing program scheme is presented as a breakthrough solution for sub-40nm FG (Floating-gate) MLC NAND flash memories and beyond. Without program speed degradation, the proposed method is able to eliminate 100% BL cell-to-cell and almost 50% WL cell-to-cell coupling interferences which are well known as a most critical scaling barrier for FG NAND flash memories.

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DO - 10.1109/VLSIC.2007.4342709

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SN - 9784900784048

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

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BT - 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers

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Park KT, Kang M, Kim D, Hwang S, Lee YT, Kim C et al. A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond. In 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. 2007. p. 188-189. 4342709. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2007.4342709

A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond

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