An 11-bit 50-MS/s pipelined ADC using circuit-sharing techniques

In this paper, an 11-bit 50-MS/s analog-to-digital converter (ADC) is presented. The sample-and-hold amplifier (SHA) and the first multiplying digital-to-analog converter (MDAC) can be efficiently combined with the proposed operational amplifier and capacitor sharing technique. In addition, the offset voltage and gain error of the operational amplifier can be reduced. The number of flash analog-to-digital converters (FADCs) can be halved by sharing comparators between the adjacent stages. The prototype ADC implemented in a 65-nm CMOS process achieves a signal-to-noise and distortion ratio of 60.7 dB and spurious-free dynamic range of 69.5 dB. The measured differential and integral nonlinearities are within ±0.6 LSB and ±1.1 LSB, respectively. The ADC occupies an active die area of 0.62 mm² and consumes 10.8 mW for a supply voltage of 1.2 V. The figure of merit is 242 fJ/conversion-step.