TY - GEN
T1 - An analog neural network processor for self-organizing mapping
AU - Sheu, Bing J.
AU - Choi, Joongho
AU - Chang, Chia Fen
N1 - Publisher Copyright:
© 1992 IEEE.
PY - 1992
Y1 - 1992
N2 - The building blocks of a self-organizing analog neural chip are shown. Its function is to evaluate the large number of dot products of the given input vectors and the stored weight vectors in a fully parallel format. Lateral competition is to be performed among the analog output voltages and the neural unit with the largest voltage level is to emerge as a single winner. Updating synapse weights is performed in a digital signal processor using an unsupervised learning rule. Design considerations addressed in the construction of the WTA (winner-take-all) circuit are: high resolution, fast operation, and layout compactness. The 4-MHz analog neural network processor chip, fabricated in a 2μm CMOS process, contains 25 neurons in the input layer and 64 neurons in the competitive layer. The behavior of the WTA circuit with only one winner for a lossy image data compression application is shown.
AB - The building blocks of a self-organizing analog neural chip are shown. Its function is to evaluate the large number of dot products of the given input vectors and the stored weight vectors in a fully parallel format. Lateral competition is to be performed among the analog output voltages and the neural unit with the largest voltage level is to emerge as a single winner. Updating synapse weights is performed in a digital signal processor using an unsupervised learning rule. Design considerations addressed in the construction of the WTA (winner-take-all) circuit are: high resolution, fast operation, and layout compactness. The 4-MHz analog neural network processor chip, fabricated in a 2μm CMOS process, contains 25 neurons in the input layer and 64 neurons in the competitive layer. The behavior of the WTA circuit with only one winner for a lossy image data compression application is shown.
UR - http://www.scopus.com/inward/record.url?scp=84939704058&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.1992.200449
DO - 10.1109/ISSCC.1992.200449
M3 - Conference contribution
AN - SCOPUS:84939704058
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 136
EP - 137
BT - Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 39th IEEE International Solid-State Circuits Conference, ISSCC 1992
Y2 - 19 February 1992 through 21 February 1992
ER -