An efficient charge recovery logic circuit

Yong Moon, Deog Kyoon Jeong

Research output: Contribution to journalArticlepeer-review

431 Scopus citations


Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-μm CMOS technology with a reduced threshold voltage of 0.2 V.

Original languageEnglish
Pages (from-to)514-522
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number4
StatePublished - Apr 1996


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